PROBLEM TO BE SOLVED: To improve strain characteristics and to reduce leaking of current to an adjoining circuit by making electron affinity of the material constituting a semiconductor layer and a difference in electron affinity in the neighborhood of interface between semiconductor layer to be specific SOLUTION: Relating to a field-effect transistor, when a lower part hetero barrier wall height between a lower part carrier supply layer 13a and a channel layer 105 is higher than an upper part hetero barrier wall height between the upper part carrier supply layer 13b and the channel layer 105, linearity in DC characteristics of the field-effect transistor improves In short, the field-effect transistor of good grain characteristics is obtained For that purpose, as a material of the lower part carrier supply layer 13b, that of smaller electron affinity than that of the upper part carrier supply layer 13b is used Hetero barrier wall height wall is decided by a difference between the channel layer 105 and the upper part carrier suppress layer 13b, or, between the channel layer 105 and the lower part carrier supply layer 13a

Field effect transistor

PURPOSE:To contrive to enhance withstand voltage of an MOS transistor by a method wherein the channel length at the bending parts at tip parts of a source region is made as longer than the other part. CONSTITUTION:The N type source region 22 and a drain region 23 are formed in a comb-shape in an N type epitaxial layer 24 on a P type Si substrate 21, and the channel region 25 are formed between them by ion implantation being controlled to have the prescribed concentration. The channel length l' of the channel region 25 at the bending parts of tip edges of the source region 22 is longer than the channel length l of the other parts (to form the shape thereof with a curve having a large radius of curvature is also favorable). By this constitution, because channel resistance at that parts are larger than the other parts, electric line of force to go from the bottoms of the drain region 23 toward the bending parts is reduced, electric field is weakened and concentration of current can be prevented. Therefore a high withstand voltage can be attained.

Mos transistor having high withstand voltage

PURPOSE:To enable high dielectric resistance by sufficiently making the curvature of a bent section of a channel formed to a tip section of a source region larger than the curvature of a bent section corresponding to a drain region. CONSTITUTION:The N type source region 22 and the drain region 23 are formed to an N epitaxial layer 24 on a P type Si substrate 21 in comblike shapes, and a P type channel 25 having predetermined concentration is molded between the regions through ion injection. The curvature R' of the bent section of the channel at the tip of the source 22 is sufficiently made larger than the curvature R of the bent section of a root of the corresponding drain 23, and the length l' of the N layer 24 up to the channel 25 from the drain 23 is made longer than the length l of other sections. Accordingly, an electric line of force proceeding toward the bent section of the channel 25 from the root of the drain 23 is lengthened, while an electric field is weakened, the concentration of currents is prevented and dielectric resistance is improved.

High dielectric resisting mos transistor

PURPOSE:To prevent current concentration and to appreciably improve drain electric strength by lengthening the length of a low-impurity density region from the tip section of a drain region to a channel region more than other sections. CONSTITUTION:An N conductive source 22, a drain region 23, an N conductive low-impurity density region 24 and a channel region 25 are formed on a P type silicon substrate 21. The source region 22 and the drain region 23 are respectively formed in combined comb shape by diffusion. The distance between the drain region 23 and channel region 25, namely the length l of the low-impurity density region 24 is formed to be shorter than the length l' of the low impurity density region 24 from the tip section of the drain region 23 to the channel region 25 (l 1.6l.

High dielectric strength high transistor

PURPOSE: To facilitate the mass production of a board product in good yield, and stabilize the performance and quality. CONSTITUTION: In this connecting board, second connectors A1 , B2 to be connected to an electric part or other electronic board used for game machine can be insert-connected to first connectors A, B fixed and connected to a plurality of circuit pattern lines in a printed board 11. A plurality of metal connecting pins 18 positioned and fixed to main bodies 14 of the first connectors A, B are inserted to a plurality of through-holes arranged in a prescribed position of each pattern line of the printed board 11, and deformed engaging parts on the terminal parts of the connecting pins 18 are engaged with the pattern lines in the continued and connected state by caulking connection to fix and connect the first connectors A, B to the printed board 11.

Connecting board for game machine or the like

PURPOSE:To raise dielectric strength by electrically connecting a base region with a source region of a double diffusing type insulating gate FET wherein the stabilization of drain current is contrived. CONSTITUTION:A base region 5 of double diffused structure is provided around a source region 4 wherein the base region is extended from a gate region 5a to a contat curface 5b with a source electrode 8. And the electrode 8 is connected with the source and base. The contact resistance with the source electrode is reduced by a high concentration layer 11. Furthermore, an increase in the amount of current is tried by widening the gate width. This structure permits the current to flow into the source region 4 through the base region 5 even if impact ionization occurs. But few current will flow into a low concentration and high resistance substrate 1. Therefore, a back gate voltage becomes small and the potential drops at the base and source regions are remarkably reduced. A forward voltage applied to a junction between the P-type base 5 and the N-type source 4 becomes small. A kink phenomenon occurring at low gate voltage will be eliminated and ON dielectric strength will be improved at high gate voltage.

High dielectric strength field effect semiconductor device

PURPOSE:To provide a double dispersion-type MOSFET which has a high withstand voltage of some 500V in terms of drain withstand voltage and has an onvoltage maintained low.

Field effect transistor with high withstand voltage

PURPOSE:To obtain the electric field effect semiconductor apparatus, having the stable high withstand voltage characteristic and the low ion voltage characteristic, by the simple manufacturing process.

Tamaoki Hiroshi

Papers

High dielectric strength field effect semiconductor device

Field effect transistor with high withstand voltage

High withstand voltage electric field effect semiconductor apparatus