This paper presents the analysis of through silicon via (TSV) with embedded capacitor for impedance tuning to improve the power integrity (PI) performance of Application-Specific Integrated Circuit – High Bandwidth Memory (ASIC-HBM) system. The crosstalk due to TSV with embedded capacitor (TSV-Cap) to signal integrity (SI) performance is evaluated by analyzing its frequency response up to 100 GHz and its eye diagram. Using this TSV-CAP, the power distribution network (PDN) impedance is kept below 50 mΩ up to 5 GHz while achieving data rate of 5 Gbps.

TSV with Embedded Capacitor for ASIC-HBM Power and Signal Integrity Improvement

Recently, mobile devices have evolved into small computers with various functions according to user requirements. Careful attention must be paid to the design of the power supply network for the stable operation of the application processor (AP), the wireless communication modem, the high performance camera, and the various interfaces of the mobile device to implement various functions of the mobile device. In this paper, we analyzed and verified the method of optimizing the design parameters such as the position, capacity, and number of decoupling capacitors to meet the target impedance required by the driver IC chip to ensure the stability of the power supply network of mobile devices that should be designed as wiring type due to mounting density limitation. The proposed wired power supply network design method can be applied to various applications including high-speed signal transmission line in addition to mobile applications.

http://koreascience.or.kr:80/article/JAKO201930968616254.pdf

Design Study for Power Integrity in Mobile Devices

For the purpose of evaluating the impact of excitation on double data rate (DDR) interface system transmission performance, a methodology for generating the worst-case excitation is proposed for signal integrity (SI) and power integrity (PI) co-simulation. The excitation is produced with the pseudo random bit sequence (PRBS) gated by a square wave of the resonant frequency of the system power distribution network (PDN). The PRBS can reflect non-ideal factors as crosstalk, reflection and loss in the signal line, and the resonant frequency of the PDN can guarantee the maximum simultaneous switching noise (SSN). A data transmission performance simulation environment of currently widely used low power double data rate SDRAM4 (LPDDR4) is constructed based on the advanced I/O buffer information specification Plus (IBIS Plus) model. Compared with the ordinary PRBS excitation, in terms of eye diagrams, the proposed worst-case excitation reduces the eye width and eye height by 4.7% and 19.9%, respectively. Further analysis also proved that 1/2 duty ratio of the gating wave can maximize the influence from the power noise. In conclusion, the proposed worst-case excitation and test environment provide an improved SI/PI co-simulation scenario for the examination of the robustness of DDR system data transmission performance.

Impact of Worst-Case Excitation for DDR interface Signal and Power Integrity Co-Simulation

As serial date rates migrate to 10Gbps and beyond, the list of signal integrity (SI) concerns and pitfalls grows. This paper focuses the design of SI of 10G serial link on OpenVPX system, and the research of the corresponding design and optimization methods based on passive design of 10Gbps high speed serial link. Combined pre-emphasis and equalization, the design enhances the quality of full link, reduces the bit error rate, and ensures accurate transmission of 10 Gbps serial signal, with margin left for system operation. With simulation and testing, the methods are verified to be accurate and feasible in this paper.

Optimization and verification of OpenVPX-based 10Gbps interconnection

In this paper, the problem of simultaneous switching noise (SSN) in the design of high-speed mixed-signal backplane is analyzed from the aspect of power integrity. How to suppress SSN of high-speed mixed-signal backplane becomes an important research direction at present. Based on the analysis of the traditional decoupling capacitor noise reduction method and the latest noise reduction principle of the electromagnetic band gap (EBG) structures, a novel type of EBG structures is proposed to suppress the noise on the printed circuit board (PCB). The simulation and measurement results show that the noise isolation depth reaches −40dB in the frequency band from 0.4 to 20GHz, which achieves the effect of ultra-wideband high isolation and meets the power and signal integrity requirements of high-speed mixed-signal backplane based on VPX(VITA 46). It provides an experimental reference for the application of the EBG structure on other high-speed mixed-signal backplane and other projects.

Power and Signal Integrity Analysis of High-speed Mixed-signal Backplanes Based on VPX

The problems confronted in the design of high-speed backplane are analyzed from the aspect of signal integrity Principles of VPX backplane and topology structure are introduced with specific analysis and design schemes provided from the aspect of stack design, place and route design, Via design etc Simulation analysis is made in the frequency domain on the signal integrity of the differential transmission line in the VPX high-speed backplane with theory of mixed-mode S-parameters

Tan Anju

Papers

Power and Signal Integrity Analysis of High-speed Mixed-signal Backplanes Based on VPX

The design and simulation of signal integrity for high-speed backplane based on VPX