A novel Parity-Preserving Reversible Gate (PPRG) is developed using Quantum-dot Cellular Automata (QCA) technology. PPRG enables rich fault-tolerance features, as well as reversibility attributes sought for energy-neutral computation. Performance of the PPRG design is validated through implementing thirteen standard combinational Boolean functions of three variables, which demonstrate from 10.7 to 41.9 percent improvement over the previous gate counts obtained with other reversible and/or preserving gate designs. Switching and leakage energy dissipation as low as 0.141 eV and 0.294 eV, for 1.5 $E_k$ energy level are achieved using PPRG, respectively. The utility of PPRG is leveraged to design a one-bit full adder with 171 cells occupying only 0.19 $\mu \text{m}^2$ area. Finally, fault detection and isolation properties are formalized into a concise procedure. PPRG-based circuits capable of self-configuring active recovery for selected three-variable standard functions are realized using a memoryless method irrespective of garbage outputs.

A Parity-Preserving Reversible QCA Gate with Self-Checking Cascadable Resiliency

Novel low power reversible binary incrementer design using quantum-dot cellular automata

Quantum Dot Cellular Automata is one of the six emerging technologies which help us to overcome the limitations of CMOS technology. Design of 4-bit ALU for AND, OR, XOR, and ADD operations using QCA is discussed through this paper. This design of 4-bit ALU using QCA is simple in structure having significantly lesser elements as compared to CMOS design. It also gives better result in terms of speed, area and power. A QCADesigner tool is used for Simulation of different components of 4 bit ALU.

Design and implementation of 4-bit arithmetic logic unit using Quantum Dot Cellular Automata

Design of image steganographic architecture using quantum-dot cellular automata for secure nanocommunication networks

Quantum-dot Cellular Automata (QCA) is one of the emerging nanotechnologies, promising an alternative to CMOS technology due to a faster speed, smaller size, lower power consumption, higher scale integration, and higher switching frequency. In addition, power dissipation is the main limitation of all the nanoelectronics design techniques including the QCA. Researchers have proposed various mechanisms to solve this problem. Among them, reversible computing is considered as a reliable solution to reduce the power dissipation. On the other hand, adders are fundamental circuits for most digital systems. So, in this paper, the focus is on designing of reversible full-adders in logical and layout levels. For this aim, the first, a method for converting irreversible functions to reversible ones is investigated. Based on it, two novel designs of reversible full-adders/subtractors are presented. In another section, a new five-input majority gate is introduced. By using of this gate, a new reversible full-adder is designed. Finally, the proposed structures are extended to design three new 8-bit reversible full-adder/subtractors. The results are indicative of the outperformance of the proposed designs in comparison with the best available ones in terms of area, complexity, delay, reversible/irreversible layout, and also in logic level in terms of garbage outputs, control inputs, number of majority and NOT gates.

New symmetric and planar designs of reversible full-adders/subtractors in quantum-dot cellular automata

Quantum-dot Cellular Automata(QCA), a promising alternative to CMOS technology, can provide a powerful and efficient computing platform for image processing which has heavy computational requirements. Image thresholding is one such image processing technique that plays a significant role in applications of image segmentation for its intuitive properties and simplicity. This work proposes an efficient architecture to carry out thresholding in image processing. It is developed around QCA technology and provides significant improvement over the existing approach.

Thresholding using Quantum-dot Cellular Automata

Quantum-dot Cellular Automata (QCA), a promising alternative to the current CMOS technology, can be a viable solution of thousands of cores in a chip in near future due to its very high device density of 1012device/cm2 and switching speeds of 10ps. On the other hand, the reversible logic is a promising computing paradigm in low power CMOS design, quantum computing, nanotechnology, and optical computing. Again, QCA consume low power which promises the energy efficient design of the logic circuits. However, the requirements of excessive logic gates and undesirable garbage outputs, while realising a function, limit the performance of a QCA based design. This work proposes a novel approach to synthesis a reversible universal QCA logic gate (RUG) structure with the target to reduce the garbage outputs as well as the logic gates of a design. This design addresses the fundamental issues of realizing reversible gates in nanotechnology and also its reliability and performance trade-off. The experimental designs establish that the RUG can ensure an energy saving, cost effective realization of QCA logic circuits that may not be possible with the conventional reversible logic gates.

Tanumoy Adak

Papers

Thresholding using Quantum-dot Cellular Automata

Synthesis of reversible universal QCA gate structure for energy efficient digital design