A mobile terminal including a body; a touchscreen provided to a front and extending to side of the body and configured to display content; and a controller configured to detect one side of the body comes into contact with one side of an external terminal, display a first area on the touchscreen corresponding to a contact area of the body and the external terminal and a second area including the content, receive an input of moving the content displayed in the second area to the first area, display the content in the first area, and share the content in the first area with the external terminal.

Mobile terminal and method for controlling the same

High-performance parallel computer architecture and systems have been improved at a phenomenal rate. In the meantime, VLSI computer-aided design (CAD) software for multibillion-transistor IC design has become increasingly complex and requires prohibitively high computational resources. Recent studies have shown that, numerous CAD problems, with their high computational complexity, can greatly benefit from the fast-increasing parallel computation capabilities. However, parallel programming imposes big challenges for CAD applications. Fully exploiting the computational power of emerging general-purpose and domain-specific multicore/many-core processor systems, calls for fundamental research and engineering practice across every stage of parallel CAD design, from algorithm exploration, programming models, design-time and run-time environment, to CAD applications, such as verification, optimization, and simulation. This journal special section will cover recent progress on parallel CAD research, including algorithm foundations, programming models, parallel architectural-specific optimization, and verification. More specifically, papers with in-depth and extensive coverage of the following topics will be considered, as well as other topics relevant to the design of parallel CAD algorithms and software tools. 1. Parallel algorithm design and specification for CAD applications 2. Parallel programming models and languages of particular use in CAD 3. Runtime support and performance optimization for CAD applications 4. Parallel architecture-specific design and optimization for CAD applications 5. Parallel program debugging and verification techniques particularly relevant for CAD The papers should be submitted via the Manuscript Central website and should adhere to standard ACM TODAES formatting requirements (http://todaes.acm.org/). The page count limit is 25.

Parallel CAD: Algorithm Design and Programming Special Section Call for Papers TODAES: ACM Transactions on Design Automation of Electronic Systems

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Design, Automation, and Test in Europe

A display apparatus includes an image processor which processes an image to display an image content; a display unit which displays thereon an image content that is processed by the image processor; and a controller which displays a user interface (UI) menu including a plurality of UI items to search the image content, as one of a two-dimensional (2D) layout by which the plurality of UI items are arranged in a 2D manner, and a three-dimensional (3D) layout by which the plurality of UI items are arranged in a 3D manner , and changes displaying the one of the layouts to display the other of the layouts according to a user's command while maintaining a continuity of the arrangement of the plurality of UI items. Accordingly, search for an image content can be efficiently performed by using a UI menu.

Display apparatus and control method thereof

Display screen or portion thereof with animated graphical user interface

In accordance with an example embodiment of the present invention, there is provided a method comprising dividing at least a part of a user interface object into a grid comprising multiple cells, associating an operation with a cell in the grid and in response to detecting an action on the cell performing the associated operation on the user interface object.

Method and apparatus for performing an operation on a user interface object

In accordance with an example embodiment of the present invention, an apparatus, method, and computer program product for: receiving a first input; initiating a zoom function in response to the first input; receiving a second input during the zoom function, wherein the second input and the first input are independent of each other;and controlling the zoom function based on the second input.

Method and apparatus for controlling a zoom function

This paper evaluates the use of pin and cycle accurate SystemC models for embedded system design exploration and early software development. The target system is the MicroBlaze VanillaNet Platform running MicroBlaze uClinux operating system. The paper compares register transfer level (RTL) hardware description language (HDL) simulation speed to the simulation speed of several different SystemC models. It is shown that simulation speed of pin and cycle accurate models can go up to 150 kHz, compared to the 100 Hz range of HDL simulation. Furthermore, utilising techniques that temporarily compromise cycle accuracy, effective simulation speed of up to 500 kHz can be obtained.

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Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

An apparatus includes an array of sub-diffraction limit-sized light receptors formed in a substrate having a light receiving surface. Each light receptor may be configured to output a scalar valued multi-bit element and to change state based on the absorption of at least one photon. The apparatus further includes an optical filter structure disposed over the light receiving surface, the optical filter structure having an array of filter pixels each having an associated passband spectral characteristic. A data element obtained from the array of sub-diffraction limit-sized light receptors is composed of a combination of a plurality of the multi-bit elements output from a plurality of light receptors that underlie filter pixels having at least two different passband spectral characteristics.

Color filters for sub-diffraction limit sensors

This paper presents a system-level approach for modelling and implementing hardware-software systems, which contain Run-Time Reconfigurable (RTR) hardware. The developed technique provides management and scheduling of RTR tasks from system-level simulations to synthesizable VHDL descriptions. The developed technique was implemented using OCAPI-xl - a system-level modelling and implementation tool based on C + + libraries. The proposed approach allows designers to explore the tradeoffs between implementation of system partitions in software, static hardware, and RTR hardware. After the system has been partitioned, an OCAPI-xl-based design flow can be utilized for implementation of all the system components.

Tero Rissa

Papers

Method and apparatus for performing an operation on a user interface object

Method and apparatus for controlling a zoom function

Evaluation of SystemC Modelling of Reconfigurable Embedded Systems

Color filters for sub-diffraction limit sensors

System-level modelling and implementation technique for run-time reconfigurable systems