Methods and apparatus are disclosed for realizing an integrated cache unit which may be flexibly used for cache system design. The preferred embodiment of the invention comprises both a cache memory and a cache controller on a single chip. In accordance with an alternative embodiment of the invention, the cache memory may be externally located. Flexible cache system design is achieved by the specification of desired cache features through the setting of appropriate cache option bits. The disclosed methods and apparatus support this user oriented approach to flexible system design. The actual setting of option bits may be peformed under software control and allows a high performance cache system to be designed with few parts, at low cost and with the ability to perform with high efficiency.

Organization of an integrated cache unit for flexible usage in cache system design

A low cost data storage and communication system. The low cost data storage and communication system has a host and at least one card connected to the host. A voltage negotiator located in the system for determining a common operating voltage range that is a common demonminator of all independent operating voltage ranges of all of the cards connected to the system. In addition, there is a novel feature of partitioning the memory storages of the card. This feature provides the host the ability to simultaneously erase any combination of sectors in a single erase group, or any combination of the entire erase groups. Another feature feature provided by this novel method of partitioning the memory storages is the ability to write protect any combination of memory groups in the card.

Voltage negotiation in a single host multiple cards system

A computer system having a cache memory subsystem which allows flexible setting of caching policies on a page basis and a line basis. A cache block status field is provided for each cache block to indicate the cache block's state, such as shared or exclusive. The cache block status field controls whether the cache control unit operates in a write-through write mode or in a copy-back write mode when a write hit access to the block occurs. The cache block status field may be updated by either a TLB write policy field contained within a translation look-aside buffer entry which corresponds to the page of the access, or by a second input independent of the TLB entry which may be provided from the system on a line basis.

Organization of an integrated cache unit for flexible usage in supporting microprocessor operations

A system and method are provided for autonomous power sequencing in a computer system. The system and method includes at least one server module such as a server blade or a server brick. A midplane receives the server modules and provides a unique address for each server module based on the location of the server modules on the midplane. The server modules each include an address module having a timer, the address module operable to obtain the unique address from the midplane and calculate a start-up time for the associated server module based on the unique address for each server module. A power supply sequences power to the server modules based on the start-up times for the server modules. Therefore, the server modules power up in a sequence instead of simultaneously and without the aid of a central controller controlling the sequencing of the powering of the server modules.

System and method for autonomous power sequencing

A system (300) and method for performing a simultaneous external read operation during internal programming of a memory device (301) is described. The memory device is configured to store data randomly and includes a source location (305), a destination location (303), a data register (307), and a cache register (309). The data register (307) is configured to simultaneously write data to the destination (303) and to the cache register (309). The system (300) further includes a processing device (107) (e.g., a microprocessor or microcontroller) for verifying an accuracy of any data received through electrical communication with the memory device. The processing device (107) is additionally configured to provide for error correction if the received data are inaccurate, add random data to the data, if required, and then transfer the error-corrected and/or random data modified data back to the destination location (303).

Simultaneous external read operation during internal programming in a flash memory device

A cache memory control apparatus according to the present invention includes data register blocks which are individually controlled for each byte, cache memory blocks, and a decoder for generating control signals which control the access to those blocks In this cache memory control apparatus, when a cache hit is made in a write mode for byte data, the control signal is supplied to the data register blocks and cache memory blocks to individually control the respective blocks, thereby allowing word data corresponding to the write byte data to be synthesized Thus, the word data can be output to an external device by one operation

Cache memory control apparatus

A method and apparatus for bus expansion, which provides a capability of transferring a data word from a first unit connected to a system bus to a second unit connected to an extension bus, with the first unit receiving a first read request input via the system bus, reading out the data word associated with the first read request, generating a first response in response to reading of the data word, and outputting the first response and the data word onto the system bus, and the second unit generating a second read request in response to an output start command supplied from a central processing unit (CPU) via the extension bus and receiving a second response and a data word from the extension bus. Responsive to the output start command supplied from the CPU, the first read request is selectively generated and output onto the system bus prior to generation of the second read request associated with the first read request. The output start command is also transferred from the CPU to the extension bus, and the data word is stored in a buffer memory responsive to a first response input via the first system bus. Responsive to the second read request input via the extension bus, the data word is selectively read out of the buffer memory and the second response is generated and outputted along with the data word onto the extension bus.

Method of and apparatus for expanding system bus

In a computer system, a board voltage reading circuit or a board voltage setting circuit is formed on a board, to effectively read and set the power voltage of the board carrying various types of circuit elements. Board identification number data and board voltage reading mode data are entered into the board voltage reading circuit, and the board voltage setting data is entered into the board voltage setting circuit. These data are entered through a support processor by a display in a console. Only when the board identification number input from support processor and board identification number preset are in agreement each other, the board voltage is read by the board voltage readig circuit. The result is displayed by the display. The board voltage setting circuit is used for setting the power voltage of the board.

Tetsu Igarashi

Papers

Cache memory control apparatus

Method of and apparatus for expanding system bus

System for reading or setting printed circuit boards voltage of computer by support processor