A method for performing fast Fourier transforms (FFTs) of various sizes simultaneously in one pipeline processor is described. The processor consists of several stages of butterfly computational elements alternated with delay-switch-delay (DSD) modules that reorder the data between the butterfly stages. By properly ordering the input data to the pipeline and the butterfly twiddle factors, the DSD operations in the pipeline can be performed in any desired sequence, enhancing fault tolerance in case of a partial failure in one or more of the DSD modules. If one of the DSDs is no longer capable of operating in its prescribed mode, it is assigned a different operating mode. All the required changes are performed by software control. It is shown that any mixture of FFTs whose sizes are powers of the pipeline's radix can be performed. For FFTs of radix 2, radix 4, and mixed 2 and 4, the principles of operation are explained and examples of timing diagrams are given. >

A pipeline processor for mixed-size FFTs

In fast Fourier transform, a necessary memory capacity is decreased, thereby decreasing a cost. The fast Fourier transform is performed on a symbol stored in a random access memory (RAM) by a butterfly operation unit in accordance with a RAM address generated by a RAM address generator. A RAM address conversion unit converts an input/output dummy address into an input/output real address by conducting bit reverse by a frequency specified in accordance with an input/output bit reverse signal, and converts a butterfly operation dummy address into a butterfly operation real address by conducting the bit reverse by a frequency specified in accordance with a butterfly operation bit reverse signal. In this manner, among output data of one symbol and input data of another symbol to be stored in the RAM subsequently to the output data of the one symbol, data having a common index indicating their orders in the symbols can be stored at the same address in the RAM. As a result, symbol input and symbol output can be overlapped.

Fast fourier transforming apparatus and method, variable bit reverse circuit, inverse fast fourier transforming apparatus and method, and ofdm receiver and transmitter

A digit reversing system is disclosed for handling mixed radix FFT operations with arbitrary arrangements of radices In a first step, all bits in an integer field of size log2 N are position reversed In a second step, subfields of the output produced in the first step are individually unreversed at the local level to produce unreversed digits The output is used for appropriately arranging input terms applied to a mixed-radix multi-stage Fast Fourier Transform (FFT) process

Digit reverse for mixed radix FFT

The present invention provides a method of performing bit or digital reversal The method comprises the step of identifying the number of points in an array to be bit-reversed or digit-reversed, and performing the bit-reversal or digit reversal using a common lookup table

Bit and digit reversal methods

Reducing the amount of required memory and instruction cycles when implementing Fast Fourier Transforms (FFTs) on a computer system is described. The invention optimizes FFT software using in-place bit reversal (IPBR) implemented on a processor capable of bit reversed incrementation. Enables the design of address generators that combine IPBR and one FFT stage in parallel. Increases efficiency by removing instructions to store output from a stand-alone IPBR mapping and then fetch the same data as input for the FFT stage.

Address generators integrated with parallel FFT for mapping arrays in bit reversed order

A fast Fourier transform (FFT) data address pre-scrambler technique and cuit for selectively generating pre-scrambled bit reversed, data address sequences needed to perform radix-2, radix-4 and mixed radix-2/4 fast Fourier transforms.

Thomas C. Choinski

Papers

Fast Fourier transform data address pre-scrambler circuit