The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

A secure communication platform on an integrated circuit is a highly integrated security processor which incorporates a general purpose digital signal processor (DSP) (62), along with a number of high performance cryptographic function elements, as well as a PCI and PCMCIA (14) interface. The secure communications platform is integrated with an off-the-shelf DSP so that a vendor who is interested in digital signal processing could also receive built-in security functions which cooperate with the DSP. The integrated circuit includes a callable library of cryptographic commands and encryption algorithms. An encryption processor is included to perform key and data encryption, as well as a high performance hash processor and a public key accelerator (28).

Cryptographic co-processor

A technique for combining biometric identification with digital certificates for electronic authentication called biometric certificates. The technique includes the management of biometric certificates through the use of a biometric certificate management system. Biometric certificates may be used in any electronic transaction requiring authentication of the participants. Biometric data is pre-stored in a biometric database of the biometric certificate management system by receiving data corresponding to physical characteristics of registered users through a biometric input device. Subsequent transactions to be conducted over a network have biometric certificates generated from the physical characteristics of a current user, which is then appended to the transaction, and which then authenticates the user by comparison against the pre-stored biometric data of the physical characteristics of users in the biometric database.

System and method for authenticating electronic transactions using biometric certificates

The present invention concerns configuration of a new category of integrated circuitry for adaptive computing. The various embodiments provide an executable information module for an adaptive computing engine (ACE) integrated circuit and may include configuration information, operand data, and may also include routing and power control information. The ACE IC comprises a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative to configure the plurality of heterogeneous computational elements for a plurality of different functional modes.

Apparatus, method, system and executable module for configuration and operation of adaptive integrated circuitry having fixed, application specific computational elements

A key management scheme for managing encryption keys in a cryptographic co-processor includes the first step of selecting a key from one of a symmetrical key type and an asymmetrical key type. Then, the key bit length is selected. The key is then generated and, lastly, the key is represented in either an external form or an internal form.

Cryptographic key management scheme

According to the present invention, the solution includes the hardware hash algorithm block to automatically generate data to hash from its initialization values and to run unassisted instead of needing a continuous supply of additional input data. This approach according to the present invention solves the above shortcomings of related solutions by eliminating the need to continuously feed input data to be hashed to obtain a high fault coverage. This reduces the sizes of the firmware and test vectors necessary to test the hardware. Also, since the hardware autonomously generates new data to hash, other hardware modules can be tested in parallel. This reduces the overall test time and cost. To remove the requirement of inputting multiple fixed length sub-blocks, additional sub-blocks are created from the initial sub-block using a hardware expansion function, and the hardware continues to run unattended for some predetermined number of sub-blocks. The hash hardware can use the expansion function, W[i]=W[i-3] xor W[i-8] xor W[i-14] xor W[i-16], to expand existing data into new data, where W[i-x] originates from the initial sub-block. By utilizing the non-linear xor function, W[i] will be random data if any of W[i-3], W[i-8], W[i-14], or W[i-16] are random. This expansion function is good for achieving high fault coverage because the new W values will likely be different from the other W values that have been hashed. This expansion function is convenient to use because it is utilized by the Secure Hash Algorithm as specified by the Secure Hash Standard FIPS PUB 180 and FIPS PUB 180-1 (includes a left rotate by one bit position).

Automatic data generation for self-test of cryptographic hash algorithms in personal security devices

An internal state machine controller in an integrated circuit containing a cryptographic implementation independently tests and verifies each of the encryption and decryption algorithms and modes within the implementation with minimal processor intervention. The cryptographic implementation automatically generates all input data and exercises all feedback modes independent of the core processor. Eliminating external test vectors results in a device less expensive to manufacture and verify. Since the cryptographic implementation tests are performed independent of the processor, other parts of the integrated circuit may be tested simultaneously with the testing of the cryptographic implementation. The processor loads in a single set of predetermined test vectors and then signals the state machine to start the testing of all the algorithms contained in the module. The output of each algorithm is used as the input of the next algorithm. The encrypted output from each algorithm is then fed back into the algorithms in reverse order and decrypted. At the end of this cycle the data returned should match the original data exactly. This is considered a cycle. The number of cycles is programmable depending on the test requirements and or fault coverage desired. In the preferred embodiment, the cryptographic implementation includes a cryptographic engine having encryption and decryption modes. Output Feedback (OFB), Electronic Codebook (ECB), Cipher Block Chaining (CBC), and Cipher Feedback (CFB) modes are supported in the preferred embodiment of the present invention.

Autotest of encryption algorithms in embedded secure encryption devices

The present invention is embodied in a Secured Processing Unit (SPU) chip, a microprocessor designed especially for secure data processing. By integrating keys, encryption/decryption engines and algorithms in the SPU, the entire security process is rendered portable and easily distributed across physical boundaries. The invention is based on the orchestration of three interrelated systems: (i) detectors, which alert the SPU to the existence, and help characterize the nature, of a security attack; (ii) filters, which correlate the data from the various detectors, weighing the severity of the attack against the risk to the SPU's integrity, both to its secret data and to the design itself; and (iii) responses, which are countermeasures, calculated by the filters to be most appropriate under the circumstances, to deal with the attack or attacks present. The present invention, with wide capability in all three of the detectors, filters and responses, allows a great degree of flexibility for programming an appropriate level of security/policy into an SPU-based application.

Thomas M. Norcross

Papers

Automatic data generation for self-test of cryptographic hash algorithms in personal security devices

Autotest of encryption algorithms in embedded secure encryption devices

Secure data processor with cryptography and avoidance of unauthorized key readout