A variable frequency clock generator. In aspects, a clock generator includes a droop detector circuit configured to monitor a voltage supply to an integrated circuit. If the supply voltage falls below a specific threshold, a droop voltage flag may be set such that a frequency-locked loop is triggered into a droop voltage mode for handling the voltage droop at the supply voltage. In response, a current control signal that is input to an oscillator that generates a system clock signal is reduced by sinking current away from the current control signal to the oscillator. This results in an immediate reduction on the system clock frequency. Such a state remains until the voltage droop has dissipated when the current path is removed for sinking some of the current.

System and method for variable frequency clock generation

The present invention relates to an average current controller, an average current control method and a buck converter using the average current controller. The average current controller includes a first comparator for generating a high H signal, a multivibrator for generating a TAVG pulse signal by receiving a high H signal outputted from the first comparator, a timing generator for generating a signal CH_ON to charge/discharge a capacitor by using at least the TAVG pulse signal, an integrator circuit unit for charging/discharging the capacitor, a second comparator for outputting a corresponding signal, an up/down counter for increasing or decreasing a counting value and a digital/analog converter for outputting by converting an output (digital signal) of the up/down counter into an analog signal.

Average current controller, average current control method and buck converter using the average current controller

A circuit for an oscillator with common-mode resonance includes a first oscillator circuit and a second oscillator circuit coupled to the first oscillator circuit. Each of the first oscillator circuit or the second oscillator circuit includes a tank circuit, a cross-coupled transistor pair, and one or more capacitors. The tank circuit is formed by coupling a first inductor with a pair of first capacitors. The cross-coupled transistor pair is coupled to the tank circuit, and one or more second capacitors are coupled to the tank circuit and the cross-coupled transistor pair. Each of the first oscillator circuit or the second oscillator circuit allows tuning of a respective common mode (CM) resonance frequency (F CM ) to be at twice a respective differential resonance frequency (F D ).

CMOS VCO with implicit common-mode resonance

A differential phase and amplitude detector circuit is presented. Two source follower circuits respectively based on NMOS and PMOS transistors are used to charge and discharge a sampling capacitor asymmetrically to provide a measurement of phase and/or amplitude difference between two signals of a substantially same frequency. The measurement can be made in one cycle, with the charging of the sampling capacitor performed during a first half cycle where a voltage difference between the two signals is positive, and the discharging during a second half cycle where a voltage difference between the two signals is negative. Biasing of the two source follower circuits enable an excess current flow between the two transistors of the two source follower circuits beyond a biasing current of the transistors to charge the sampling capacitor during the first half cycle, and disable the excess current flow between the two transistors during the second half cycle.

Differential Phase and amplitude detector

A flip-flop includes a conditional boosting stage, a pulse generator and a latch. The conditional boosting stage includes a boosting capacitor, and is configured to pre-charge the boosting capacitor in accordance with a previous output signal and boost a node connected to the boosting capacitor upon a level of the previous output signal being different from a level of a current input signal. The pulse generator is configured to generate a pulsed signal in accordance with transitions of a clock signal. The latch configured is to latch the current input signal to a current output signal in accordance with the pulsed signal.

Flip-flop and driving method thereof

Methods and circuits for CMOS relaxation oscillators are disclosed. A single capacitive element, a single current source and a switching network are utilized. A switching network of the oscillator allows both nodes of the capacitive element to rise and fall between a positive and a negative voltage with respect to ground supply, without causing leakage to substrate or risk of latch-up, i.e. the inadvertent creation of a low-impedance path. The oscillator requires minimum silicon area, has an improved duty cycle, is particular useful for implementing lower frequency clocks and is enabled for smaller technology nodes, lower than 250 nm, due to lower supply voltage.

Tim Morris

Papers

Area efficient single capacitor CMOS relaxation oscillator