An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Automated processor generation system for designing a configurable processor and method for the same

An intelligent network interface card (INIC) or communication processing device (CPD) works with a host computer for data communication. The device provides a fast-path that avoids protocol processing for most messages, greatly accelerating data transfer and offloading time-intensive processing tasks from the host CPU. The host retains a fallback processing capability for messages that do not fit fast-path criteria, with the device providing assistance such as validation even for slow-path messages, and messages being selected for either fast-path or slow-path processing. A context for a connection is defined that allows the device to move data, free of headers, directly to or from a destination or source in the host. The context can be passed back to the host for message processing by the host. The device contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors devoted to transmit, receive and utility processing, providing full duplex communication for four Fast Ethernet nodes.

TCP/IP offload network interface device

Controlled devices according to a device control model maintain a state table representative of their operational state. Devices providing a user control point interface for the controlled device obtain the state table of the controlled device, and may also obtain presentation data defining a remoted user interface of the controlled device and device control protocol data defining commands and data messaging protocol to effect control of the controlled device. These user control devices also subscribe to notifications of state table changes, which are distributed from the controlled device according to an eventing model. Accordingly, upon any change to the controlled device's operational state, the eventing model synchronizes the device's state as represented in the state table across all user control devices.

Synchronization of controlled device state using state table and eventing in data-driven remote device control model

A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU. A preferred embodiment includes a trio of pipelined processors with separate processors devoted to transmit, receive and management processing, with full duplex communication for four fast Ethernet nodes.

Fast-path apparatus for receiving data corresponding to a TCP connection

A general programmatic interface-to-network messaging adapter exposes a suitable object integration interface or application programming interface to applications on a controller device and sends network data messages to invoke services or query status of a controlled device. The adapter maps application calls to the interface into network data messages according to service protocols of the controlled device. The general adapter provides the interface suitable to any specific service of a controlled device based on a data description of the interface, and converts the application calls to network data messages based on a data description of a protocol and format for network data messages to interact with the specific service. Once the interface/messaging description is obtained, applications on the controller device can programmatically interact with the adapter, and the adapter then handles appropriate message exchanges with the service of the controlled device. The general adapter allows controller device applications to be written using object-oriented programming, while avoiding code download.

Data driven remote device control model with general programming interface-to-network messaging adapter

A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects

A system and method for sending and receiving data with a reliable communication protocol. The system includes a computer at a node having a backplane, a CPU board plugged into the backplane, software instructions for the CPU, and a special network board plugged into the backplane. The CPU board, software, and network card act to implement the TCP/IP protocol suite. The network card or board includes an interface to receive data packets from the physical layer, and circuitry to verify the TCP checksum before de-encapsulation and routing of the TCP segment by the network layer software. It also includes circuitry to automatically prepare the acknowledgement signal to be sent by the receiving computer to the sending computer. It additionally includes circuitry to calculate the error detecting code on outgoing signals from the sending computer to the receiving computer.

System for transmitting and receiving data within a reliable communications protocol by concurrently processing portions of the protocol suite

Apparatus and method for constructing data for transmission within a reliable communication protocol by performing portions of the protocol suite concurrently

The wide use of standard packet telemetry protocols based on the Consultative Committee for Space Data Systems (CCSDS) recommendations in future space science missions has created a large demand for low-cost ground CCSDS processing systems. Some of the National Aeronautics and Space Administration (NASA) missions using CCSDS telemetry include Small Explorer, Earth Observing System (EOS), Space Station, and Advanced Composite Explorer . For each mission, ground telemetry systems are typically used in a variety of applications including spacecraft development facilities, mission control centers, science data processing sites, tracking stations, launch support equipment, and compatibility test systems . The future deployment of EOS spacecraft allowing direct broadcast of data to science users will further increase demand for such systems. For the last ten years, the Data Systems Technology Division (DSTD) at NASA Goddard Space Flight Center (GSFC) has been applying state-of-the-art commercial Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC) technology to further reduce the cost of ground telemetry data systems . As a continuation of this effort, a new desktop CCSDS processing system is being prototyped that offers up to 150 Mbps performance at a replication cost of less than $20K. This system acts as a gateway that captures and processes CCSDS telemetry streams and delivers them to users over standard commercial network interfaces . This paper describes the development of this prototype system based on the Peripheral Component Interconnect (PCI) bus and 0.6 micron complementary metal oxide semiconductor (CMOS) ASIC technology . The system performs frame synchronization, bit transition density decoding, cyclic redundancy code (CRC) error checking, Reed-Solomon decoding, virtual channel sorting/filtering, packet extraction, and quality annotation and accounting at data rates up to and beyond 150 Mbps.

A very low cost 150 mbps desktop ccsds gateway

A programmable circuit assembly and methods for high bandwidth data processing. The assembly includes an array of in-circuit programmable logic packages interconnected with an array of memory packages, allowing for elastic buffering of data in a variety of directions. Each programmable package includes package leads, a memory, and output drivers. Each output driver is connected to a respective package lead, which is configured to generate a logic function defined by programming data stored in the memory. A method includes storing programming data for operating the assembly to send signals on different paths between a programmable package and a memory package.

Toby D. Bennett

Papers

System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects

System for transmitting and receiving data within a reliable communications protocol by concurrently processing portions of the protocol suite

Apparatus and method for constructing data for transmission within a reliable communication protocol by performing portions of the protocol suite concurrently

A very low cost 150 mbps desktop ccsds gateway

Programmable circuit assembly and methods for high bandwidth data processing