A method for decoding a plurality of flash memory cells which are error-correction-coded as a unit, the method comprising providing a hard-decoding success indication indicating whether or not hard-decoding is at least likely to be successful; and soft-decoding the plurality of flash memory cells at a first resolution only if the hard-decoding success indication indicates that the hard-decoding is not at least likely to be successful.

Flash memory apparatus and methods using a plurality of decoding stages including optional use of concatenated BCH codes and/or designation of “first below” cells

The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The preferred IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications.

Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements

A system and method in accordance with the present invention determines in real-time the portions of a set of characters from a data or character stream which satisfies one or more predetermined regular expressions. A Real-time Deterministic Finite state Automaton (RDFA) (250) ensures that the set of characters is processed at high speeds with relatively small memory requirements. An optimized state machine models the regular expression(s) and state related alphabet lookup (254) and next state (256) tables are generated. Characters from the data stream (205) are processed in parallel using the alphabet lookup (254) and next state (256) tables, to determine whether to transition to a next state or a terminal state, until the regular expression is satisfied or processing is terminated. Additional means may be implemented to determine a next action from satisfaction of the regular expression.

High speed data stream pattern recognition

Flash memory apparatus including a plurality of memory portions, and a controller operative to reserve for data retention purposes, for at least a first duration of time, only certain portions from among said plurality of memory portions including allocating data, during the first duration of time, only to the certain portions, thereby to define at least one of the plurality of memory portions other than the certain portions as a retired memory portion for the first duration of time.

Systems and methods for temporarily retiring memory portions

A system for storing a plurality of logical pages in a set of at least one flash device, each flash device including a set of at least one erase block, the system comprising apparatus for distributing at least one of the plurality of logical pages over substantially all of the erase blocks in substantially all of the flash devices, thereby to define, for at least one logical page, a sequence of pagelets thereof together including all information on the logical page and each being stored within a different erase block in the set of erase blocks; and apparatus for reading each individual page from among the plurality of logical pages including apparatus for calling and ordering the sequence of pagelets from different erase blocks in the set of erase blocks.

Systems and methods for averaging error rates in non-volatile devices and storage systems

A programmable logic device, such as a digital signal processor (DSP) ( 130 ), having a Chien search unit ( 116 ) is disclosed. The Chien search unit ( 116 ) is arranged to perform finite field arithmetic functions useful in identifying roots of a polynomial, as is useful in Reed-Solomon decoding, particularly, after the execution of a Euclidean array function. Galois field multipliers ( 306 ) perform finite field multiplication of coefficient values (Λ) and powers of symbol values (α); the products of such multiplications are written into the coefficient register ( 304 ) for use in connection with the next symbol value. Finite field adders ( 308, 310; 318, 320 ) produce a final sum that is interrogated by zero detection circuitry ( 206 ) to determine whether a root is presented by the current symbol value. The provision of a Chien search execution unit ( 116 ) provides important efficiency so as to enable programmable logic devices, such as digital signal processors ( 130 ) and microprocessors to effect Reed-Solomon decoding.

Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding

A programmable, reconfigurable Reed-Solomon encoder/decoder allows for flexible reprogramming of encoders and decoders for a variety of applications. The standard Reed-Solomon parameters of the Galois Field order, the primitive polynomial, the number of symbols for each codeword of the transmitted and source data are settable via writable registers. The Reed-Solomon encoder/decoder may be coupled to a digital signal processor which specifies the parameters loaded in the writable registers via data register space of data memory space. The decoder and encoder parameters are separately specified and the decoder and encoder can run simultaneously and independently.

Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder

A method for decoding a codeword in a data stream encoded according to a low density parity check (LDPC) code having an m×j parity check matrix H by initializing variable nodes with soft values based on symbols in the codeword, wherein a graph representation of H includes m check nodes and j variable nodes, and wherein a check node m provides a row value estimate to a variable node j and a variable node j provides a column value estimate to a check node m if H(m,j) contains a 1, computing row value estimates for each check node, wherein amplitudes of only a subset of column value estimates provided to the check node are computed, computing soft values for each variable node based on the computed row value estimates, determining whether the codeword is decoded based on the soft values, and terminating decoding when the codeword is decoded

Method and System for Decoding Low Density Parity Check Codes

The addition of a specialized instruction to perform the MAX star function provides a way to get better performance turbo decoding on a digital signal processor. A subtractor forms the difference between inputs A and B. The sign of this difference controls a multiplexer selection of the max function maximum of inputs A and B. The difference is applied to a lookup table built to handle both positive and negative inputs. The look up table output is summed with with the difference to form the MAX star result. The size of the lookup table is selected to match the required resolution.

DSP instruction for turbo decoding

A programmable logic device ( 130 ) as may be used in a communication system device such as a digital subscriber line modem ( 408 ) to perform Reed-Solomon decoding upon a received frame of digital values is disclosed. The programmable logic device ( 130 ) may be implemented as a DSP ( 130 ) or a general purpose microprocessor, for example. According to one disclosed embodiment of the invention, a group of look-up tables ( 60 ) are arranged, each look-up table ( 60 ) associated with one of the possible power values of a finite field, number up to twice the number of correctable errors. The contents of each entry (SYN) of the look-up tables ( 60 ) correspond to the finite field (e.g., Galois field) multiplication of a primitive element raised to an index power with a character of the finite field alphabet. Galois field multiplications ( 62 ) in syndrome accumulation may now be performed with a single table look-up operation. According to other disclosed embodiments of the invention, look-up tables ( 60, 160 ) are similarly arranged to contain the contents of finite field (e.g., Galois field) multiplication products for use in a Chien search procedure. In a single-thread version of the disclosed Chien search procedure, a subset of the same look-up tables ( 60 ) as used in syndrome accumulation may be utilized.

Tod D. Wolf

Papers

Efficient hardware implementation of chien search polynomial reduction in reed-solomon decoding

Programmable, reconfigurable DSP implementation of a Reed-Solomon encoder/decoder

Method and System for Decoding Low Density Parity Check Codes

DSP instruction for turbo decoding

Efficient look-up table methods for Reed-Solomon decoding