The twisted torus processing surface, introduced and analyzed by Martin,1,2 is extended to contain a double twist and then mapped into a two-dimensional network suitable for implementation on a VLSI wafer. The result is a homogeneous, isotropic multiprocessor configuration without boundaries. Every processor has four nearest neighbors, and the interconnections between all pairs of processors are of approximately equal length. Special attention is given to mapping binary trees onto the processor array. Most divide-and-conquer-type problems will distribute themselves relatively uniformly over all available processors. Nine building blocks are introduced that will permit making doubly twisted torus arrays of arbitrary sizes.

Double twisted torus networks for VLSI processor arrays

Recent advances in computing allow taking new look at matrix multiplication, where the key ideas are: decreasing interest in recursion, development of processors with thousands (potentially millions) of processing units, and influences from the Algebraic Path Problems. In this context, we propose a generalized matrix-matrix multiply-add (MMA) operation and illustrate its usability. Furthermore, we elaborate the interrelation between this generalization and the BLAS standard.

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Generalizing matrix multiplication for efficient computations on modern computers

A new linear transform for scrambling images is proposed in this paper. The forward transform scrambles the image and the inverse transform unscrambles the image. We define transformation matrices for both scalar and blocked cases. Recursive and non-recursive algorithms based on the new transform are also proposed. The degree of scrambling or unscrambling can be determined by the user. The experimental results show that the positions of the pixels are strongly irregularized using the proposed transform. Unscrambling using a wrong key fails and results in an unintelligible image which cannot be recognized. We also show that the new transform provides a high level of image scrambling and is robust under common attacks and noise. The proposed linear transform is very simple and its implementation as triple-matrix multiplication is straightforward.

Image scrambling based on a new linear transform

In this paper we propose a novel “Mesh-of-Tori” cellular interconnection network for scalable and massively parallel array processors with frontal plane I/O. The unit (called “m-Cell”) in this topology is the smallest double (for 2D case) or triple (for 3D) folded torus, which forms the basic ‘tile’. The Cells can be repeated and “fused” to form macro-Cells, or “divided” to form smaller Cells, without destroying the homogeneity of the entire structure, to give a highly scalable and cellular “Mesh-of-Tori” topology. The key features of the proposed interconnection network are (1) an excellent up and down scalability due to regularity and modularity, (2) no end-around connections, and (3) capability to map 2D streaming data from frontal plane I/O (stacked layer of sensors) to the processing elements. We also provide solutions for stream data manipulation through frontal plane I/O, on the propose d cellular topology.

Mesh-of-Tori: A Novel Interconnection Network for Frontal Plane Cellular Processors

Sparse storage formats describe a way how sparse matrices are stored in a computer memory. Extensive research has been conducted about these formats in the context of performance optimization of the sparse matrix-vector multiplication algorithms, but memory efficient formats for storing sparse matrices are still under development, since the commonly used storage formats (like COO or CSR) are not sufficient. 
In this paper, we propose and evaluate new storage formats for sparse matrices that minimize the space complexity of information about matrix structure.
The first one is based on arithmetic coding and the second one is based on binary tree format. We compare the space complexity of common storage formats and our new formats and prove that the latter are considerably more space efficient.

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Tree-based Space Efficient Formats for Storing the Structure of Sparse Matrices

The two-dimensional (2D) forward/inverse discrete Fourier transform (DFT), discrete cosine transform (DCT), discrete sine transform (DST), discrete Hartley transform (DHT), discrete Walsh-Hadamard transform (DWHT), play a fundamental role in many practical applications. Due to the separability property, all these transforms can be uniquely defined as a triple matrix product with one matrix transposition. Based on a systematic approach to represent and schedule different forms of the $n\times n$ matrix-matrix multiply-add (MMA) operation in 3D index space, we design new orbital highly-parallel/scalable algorithms and present an efficient $n\times n$ unified array processor for computing {\it any} $n\times n$ forward/inverse discrete separable transform in the minimal $2n$ time-steps. Unlike traditional 2D systolic array processing, all $n^2$ register-stored elements of initial/intermediate matrices are processed simultaneously by all $n^2$ processing elements of the unified array processor at each time-step. Hence the proposed array processor is appropriate for applications with naturally arranged multidimensional data such as still images, video frames, 2D data from a matrix sensor, etc. Ultimately, we introduce a novel formulation and a highly-parallel implementation of the frequently required matrix data alignment and manipulation by using MMA operations on the same array processor so that no additional circuitry is needed.

Toshiaki Myiazaki

Papers

Orbital Algorithms and Unified Array Processor for Computing 2D Separable Transforms