Beyond energy, the growing number of defects in physical substrates is becoming another major constraint that affects the design of computing devices and systems. As the underlying semiconductor technologies are getting less and less reliable, the probability that some components of computing devices fail also increases, preventing designers from realizing the full potential benefits of on-chip exascale integration derived from near atomic scale feature dimensions. As the quest for performance confronts permanent and transient faults, device variation, and thermal issues, major breakthroughs in computing efficiency are expected to benefit from unconventional and new models of computation, such as brain-inspired computing. The challenge is then to find not only high-performance and energy-efficient, but also fault-tolerant computing solutions. Neural computing principles remain elusive, yet as source of a promising fault-tolerant computing paradigm. In the quest to fault tolerance can be translated into scalable and reliable computing systems, hardware design itself and/or to use circuits even with faults has further motivated research on neural networks, which are potentially capable of absorbing some degrees of vulnerability based on their natural properties. This paper presents a survey on fault tolerance in neural networks manly focusing on well-established passive techniques to exploit and improve, by design, such potential but limited intrinsic property in neural models, particularly for feedforward neural networks. First, fundamental concepts and background on fault tolerance are introduced. Then, we review fault types, models, and measures used to evaluate performance and provide a taxonomy of the main techniques to enhance the intrinsic properties of some neural models, based on the principles and mechanisms that they exploit to achieve fault tolerance passively. For completeness, we briefly review some representative works on active fault tolerance in neural networks. We present some key challenges that remain to be overcome and conclude with an outlook for this field.

Fault and Error Tolerance in Neural Networks: A Review

The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA's configurable logic blocks (CLBs). The defects affecting the FPGA's interconnection resources can also be tolerated with a high probability. This method is suited for the makers, since the yield of the chip is considerably improved, specially for large sizes. On the other hand, defect-free chips can be used as either maximum size, ordinary array chips or fault tolerant chips. In the fault tolerant chips, the users will be able to achieve directly the fault tolerance by only shifting the design data automatically, without changing the physical design of the running application, without loading other configurations data from the off-chip FPGA, and without the intervention of the company. For tolerating defective resources, the use of spare CLBs is required. In this paper, two possibilities for distributing the spare resources (king-shifting and horse-allocation) are introduced and compared.

Defect and fault tolerance FPGAs by shifting the configuration data

Topics related to the faults in SRAM-based field programmable gate arrays (FPGAs) have been intensively studied in recent research studies. These topics include FPGA fault detection, FPGA fault diagnosis, FPGA defect tolerance, and FPGA fault tolerance. This paper provides a guided tour to the approaches related to these topics. These include techniques, which are applied to the FPGA and others which have been recently introduced and can be applied to today's FPGAs.

Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey

This paper presents a new design for testing SRAM based field programmable gate arrays (FPGAs) The new proposed method is able to test both the configurable logic blocks (CLBs) and the interconnection networks The proposed design is based on slightly modifying the original SRAM part in the FPGA so that it will allow the configuration data to be looped on a chip and then the test becomes easier This method requires a very short test time compared to the previous works Moreover, the off-chip memory used in the storage of the configurations data is considerably reduced The application of this method to the XC4000 family and ORCA shows that (relative to that required by the previous works) the test time can be reduced by 872% and the required off-chip memory can be reduced by 886%

Testing the logic cells and interconnect resources for FPGAs

This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original SRAM part is modified a bit so that the FPGA gets the ability to automatically shift the data on-chip and then the test becomes faster. This method does not need a large outside memory (off-chip memory) for saving the test data. It is proved that this method detects multiple faults and covers 100%; of modeled faults. The simulation results of Xilinix XC4000 family, using CAD tools, shows that the routing and the placement of this method are easily achieved.

Design of an automatic testing for FPGAs

In this paper, a constructive algorithm for fault tolerant feedforward neural network, called FTCA, is proposed The algorithm starts with a network with a single hidden neuron, and a new hidden unit is added to the network whenever it fails to converge Before inserting the new hidden neuron into the network, only the weights connecting the new hidden neuron to the other neurons are trained (ie updated) until there is no significant reduction of the output error To generate a fault tolerant network, the relevance of synaptic weights is estimated in each cycle And only the weights which have a relevance less than a specified threshold are updated in that cycle The loss of connections between neurons (which are equivalent to stuck-at-0 faults) are assumed The simulation results indicate that the network constructed by FTCA has a significant fault tolerance ability

Fault tolerant constructive algorithm for feedforward neural networks

Dynamic Constructive Fault Tolerant Algorithm for Feedforward Neural Networks

This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA’s SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases. key words: field programmable gate array (FPGA), testing, design for testing, shifting configurations

Toshiaki Ohmameuda

Papers

Design of an automatic testing for FPGAs

Fault tolerant constructive algorithm for feedforward neural networks

Dynamic Constructive Fault Tolerant Algorithm for Feedforward Neural Networks

Fast testable design for SRAM-based FPGAs