A capacitor structure for an integrated circuit and a method of fabrication are described. The capacitor structure is defined by layers forming interconnect metallization and interlayer dielectrics. The latter are relatively thick, and provide high breakdown voltages. Multilevel metallization schemes allow for a stack of a plurality of electrodes to be provided. The electrodes may take the form of stacks of flat plates interconnected in parallel so that the capacitance is the sum of capacitances of alternate layers in the stack. Advantageously each electrode comprises a main portion and a surrounding portion having the form of a protecting ring, coplanar with the main portion of the electrode. The ring prevents thinning of the dielectric near edges of electrode during fabrication, to improve control of breakdown voltages for high voltage applications. Alternative electrode structures employing a plurality of interconnected fingers, and particularly a configuration having interdigitated fingers, are provided to increase the capacitance per unit surface area. Parallel electrode fingers are stacked in vertical alignment, or offset, and interconnected to provide vertical, horizontal or inclined stacks having different patterns of polarities, thereby forming capacitors of various configurations. The capacitor structures have particular application for high voltage (>100 V), low leakage and high frequency (MHz/GHz) applications.

Capacitor structure for an integrated circuit

At least one semiconductor fin for a capacitor is formed concurrently with other semiconductor fins for field effect transistors. A lower conductive layer is deposited and lithographically patterned to form a lower conductive plate located on the at least one semiconductor fin. A dielectric layer and at least one upper conductive layer are formed and lithographically patterned to form a node dielectric and an upper conductive plate over the lower conductive plate as well as a gate dielectric and a gate conductor over the other semiconductor fins. The lower conductive plate, the node dielectric, and the upper conductive plate collectively form a capacitor. The finFETs may be dual gate finFETs or trigate finFETs. A buried insulator layer may be optionally recessed to increase the capacitance. Alternately, the lower conductive plate may be formed on a planar surface of the buried insulator layer.

FinFET-compatible metal-insulator-metal capacitor

This invention is directed to a semiconductor memory device including a storage element comprising a ferroelectric material or a capacitor dielectric material between a top (plate) electrode and a bottom (stack) electrode. In particular, the invention pertains to the design and fabrication of the stack electrode, which is described as compound because it is comprised of two or more materials which are either patterned separately (with at least one material being deposited and patterned prior to the deposition of the others), or arranged so that each of the component materials significantly contributes to the area over which the ferroelectric or capacitor dielectric is initially deposited. These compound stack electrodes may offer ease in processing, more economical use of noble metal materials, and potentially increased mechanical stability (e.g., resistance to hillocking) relative to solid, single-material electrodes of the same dimensions.

Compound electrode stack capacitor

A method and apparatus if provided for shielding a capacitor structure formed in a semiconductor device. In a capacitor formed in an integrated circuit, one or more shields are disposed around layers of conductive strips to shield the capacitor. The shields confine the electric fields between the limits of the shields.

Shielded capacitor structure

A dynamic random access memory (DRAM) cell having a corrugated storage contact capacitor for enhancing capacitance. A noncritical alignment is effected between the substrate contact area and the lower capacitor plate by using an etch stop layer to protect wordlines, field-effect transistors (FETs), and field oxide regions during the patterning and etching of storage capacitor regions. The corrugated storage contact capacitor is fabricated by depositing alternating layers of dielectric materials having either substantially different etch rates or wet etch selectivity one toward the other. The layers are isotropically etched and a cavity having corrugated sidewalls is provided. A doped poly layer is deposited to function as the storage-node capacitor plate. The deposition of a dielectric layer is followed by an insitu-doped poly layer deposited to form the upper capacitor plate. The capacitor thus formed is typified as having the storage-node capacitor plate self-aligned to the contact area of the substrate.

Corrugated storage contact capacitor and method for forming a corrugated storage contact capacitor

In a stacked capacitor cell structure of a semiconductor memory device, the MIM (metal-insulator-metal) capacitor to be used as a transfer gate comprises at least a unit stack of a first insulation film, a lower capacitor electrode, a capacitor gate insulation film, an upper capacitor electrode, another capacitor gate insulation film and an extension of the lower capacitor electrode. Thus, the surface area of the lower capacitor electrode can be enlarged without increasing the plane area exclusively occupied by memory cells. Moreover, with such a configuration, since the surface area of the lower capacitor electrode can be augmented without increasing the film thickness of the electrode, the technical difficulties that the currently known methods of manufacturing semiconductor memory devices with a stacked capacitor cell structure encounter are effectively eliminated and consequently troubles such as short-circuited lower capacitor electrodes become non-existent.

Toshiharu Watanabe

Papers

Semiconductor memory device having a stacked capacitor cell structure