An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

In fabricating a thin film transistor, an active layer comprising a silicon semiconductor is formed on a substrate having an insulating surface Hydrogen is introduced into The active layer A thin film comprising SiO x N y is formed to cover the active layer and then a gate insulating film comprising a silicon oxide film formed on the thin film comprising SiO x N y  Also, a thin film comprising SiO x N y is formed under the active layer The active layer includes a metal element at a concentration of 1×10 15 to 1×10 19 cm −3 and hydrogen at a concentration of 2×10 19 to 5×10 21 cm −3 

Semiconductor device and method for forming the same

An active matrix display device having a pixel structure in which pixel electrodes, gate wirings and source wirings are suitably arranged in the pixel portions to realize a high numerical aperture without increasing the number of masks or the number of steps. The device comprises a gate electrode and a source wiring on an insulating surface, a first insulating layer on the gate electrode and on the source wiring, a semiconductor layer on the first insulating film, a second insulating layer on the semiconductor film, a gate wiring connected to the gate electrode on the second insulating layer, a connection electrode for connecting the source wiring and the semiconductor layer together, and a pixel electrode connected to the semiconductor layer.

Semiconductor Device and Method of Fabricating the Same

An apparatus for exposing a pattern, formed on a mask, on each of a plurality of partitioned areas on a photosensitive substrate by a step-and-repeat scheme includes a projection optical system for projecting the pattern of the mask on the photosensitive substrate, a substrate stage for holding the photosensitive substrate and two-dimensionally moving the photosensitive substrate within a plane perpendicular to the optical axis of the projection optical system, a detection unit for projecting a pattern image having a predetermined shape on the photosensitive substrate and photoelectrically detecting light reflected by the photosensitive substrate to detect a position at each of a plurality of points on the photosensitive substrate along the optical axis of the projection optical system, and a measurement unit for, when each of a plurality of measurement points in a partitioned area on which a pattern of the mask is to be exposed next coincides with or approaches the pattern image, detecting an offset amount between an imaging plane of the projection optical system and the next partitioned area along the optical axis during a stepping operation of the substrate stage, wherein the imaging plane and the next partitioned area are relatively moved along the optical axis in accordance with the measured offset amount before the pattern of the mask is exposed on the next partitioned area.

Exposure method and apparatus

The present invention meets these needs by providing improved methods of filling gaps. In certain embodiments, the methods involve placing a substrate into a reaction chamber and introducing a vapor phase silicon-containing compound and oxidant into the chamber. Reactor conditions are controlled so that the silicon-containing compound and the oxidant are made to react and condense onto the substrate. The chemical reaction causes the formation of a flowable film, in some instances containing Si—OH, Si—H and Si—O bonds. The flowable film fills gaps on the substrates. The flowable film is then converted into a silicon oxide film, for example by plasma or thermal annealing. The methods of this invention may be used to fill high aspect ratio gaps, including gaps having aspect ratios ranging from 3:1 to 10:1.

CVD flowable gap fill

In a first region of a semiconductor substrate, there are formed MIS transistors each composed of a gate insulating film, a gate electrode, and source/drain regions. In a second region of the semiconductor substrate, there is formed an impurity diffusion layer serving as a conductive layer. On an interlayer insulating film, there are formed an antenna interconnection connected to the gate electrodes and an interconnection for charge dissipation connected to the conductive layer. During the process of dry etching for forming the interconnections, charges move into the semiconductor substrate via the interconnection for charge dissipation. The deterioration of the gate insulating film caused by the injection of charges into the gate electrode is suppressed and the degradation of characteristics of the MIS transistor including a shift in threshold is also suppressed. Even in the case where a floating interconnection region is present contiguously to the antenna interconnection, the provision of the interconnection for charge dissipation reduces the amount of shift in the threshold of each of the MIS transistors and equalizes the respective thresholds of the MIS transistors.

MIS device, method of manufacturing the same, and method of diagnosing the same

An element isolator is formed in a silicon substrate. A gate oxide film and a gate electrode are formed overlying the silicon substrate. Subsequently, a four-step large-tilted-angle ion implant is performed in which ions of nitrogen are implanted at an angle of tilt of 25 degrees, to form an oxynitride layer at each edge of the gate oxide film and to form a nitrogen diffusion layer in the silicon substrate. This is followed by formation of a lightly-doped source/drain region by means of impurity doping. A sidewall is formed on each side surface of the gate electrode, which is followed by formation of a heavily-doped source/drain region by impurity doping. The present invention provides an improved semiconductor device having high-performance, highly-reliable MOS field effect transistors and a method for fabricating the same.

Method for fabricating a semiconductor device having a nitrogen diffusion layer

A method of fabricating a field effect transistor, wherein impurity diffusion layers of source and drain are formed by an ion implantation method using the gate electrode as the mask by inclining the semiconductor substrate with respect to the ion beam incident direction so as to prevent the channeling effect and also rotating it in planarity with respect to the ion beam scanning plane. As a result, impurity diffusion layers can be formed symmetrically with respect to the gate electrode.

Method of making symmetrically controlled implanted regions using rotational angle of the substrate

After P+ ions are implanted into a polysilicon film in an nMOSFET region, a heat treatment is performed to diffuse phosphorus down to the lower part of the polysilicon film The diffusion reduces the concentration of phosphorus in an upper end portion of the polysilicon film and inhibits the upper end edges of a gate electrode from being increased in size during patterning Then, B+ ions are implanted into the polysilicon film in a pMOSFET region and the polysilicon film is etched into a gate configuration Since a heat treatment for simultaneously diffusing phosphorus and boron in the polysilicon film is not performed, the entrance of boron from the gate electrode into a semiconductor substrate is inhibited, while the occurrence of side etching during the formation of an n-type polysilicon gate is suppressed

Method of fabricating semiconductor device

A polysilicon electrode is formed in an active area surrounded by an isolation on a silicon substrate with a gate oxide film sandwiched therebetween, a polysilicon wire is formed on the isolation, and a source/drain region is formed on both sides of the polysilicon electrode. On the both sides of a polysilicon film constituting the electrode and the wire are formed side walls having a height that is 4/5 or less of the height of the polysilicon film. Furthermore, the polysilicon film is provided with a silicide layer in contact with the top surface and portions of the side surfaces of the polysilicon film projecting from the side walls, and another silicide layer is formed in contact with the source/drain region. Since the sectional area of the silicide layer is increased, the resistance value can be suppressed even when the dimension of the polysilicon film is minimized. Thus, the invention provides a semiconductor device including an FET having a low resistance value applicable to a refined pattern.

Toshiki Yabu

Papers

MIS device, method of manufacturing the same, and method of diagnosing the same

Method for fabricating a semiconductor device having a nitrogen diffusion layer

Method of making symmetrically controlled implanted regions using rotational angle of the substrate

Method of fabricating semiconductor device

Semiconductor device having polysilicon electrode minimization resulting in a small resistance value