A system and method for generating context vectors for use in storage and retrieval of documents and other information items. Context vectors represent conceptual relationships among information items by quantitative means. A neural network operates on a training corpus of records to develop relationship-based context vectors based on word proximity and co-importance using a technique of "windowed co-occurrence". Relationships among context vectors are deterministic, so that a context vector set has one logical solution, although it may have a plurality of physical solutions. No human knowledge, thesaurus, synonym list, knowledge base, or conceptual hierarchy, is required. Summary vectors of records may be clustered to reduce searching time, by forming a tree of clustered nodes. Once the context vectors are determined, records may be retrieved using a query interface that allows a user to specify content terms, Boolean terms, and/or document feedback. The present invention further facilitates visualization of textual information by translating context vectors into visual and graphical representations. Thus, a user can explore visual representations of meaning, and can apply human visual pattern recognition skills to document searches.

System and method of context vector generation and retrieval

A fault-tolerant storage device array using a copyback cache storage unit for temporary storage. When a Write occurs to the RAID system, the data is immediately written to the first available location in the copyback cache storage unit. Upon completion of the Write to the copyback cache storage unit, the host CPU is immediately informed that the Write was successful. Thereafter, further storage unit accesses by the CPU can continue without waiting for an error-correction block update for the data just written. In a first embodiment of the invention, Read-Modify-Write operations are performed during idle time. In a second embodiment of the invention, normal Read-Modify-Write operation by the RAID system controller continue use Write data in the controller's buffer memory. In a third embodiment, at least two controllers, each associated with one copyback cache storage unit, copy Write data from controller buffers to the associated copyback cache storage unit. If a copyback cache storage unit fails, more than one controller share a single copyback storage unit. In a fourth embodiment, Write data is copied from a controller buffer to a reserved area of each storage unit comprising the array.

Storage device array architecture with copyback cache

A system, method and computer readable medium are disclosed for reducing power consumption in clusters, grids, on-demand centers, and so forth. The principles disclosed herein can reduce both direct and indirect power consumption while maintaining either full cluster performance or adequate SLA based cluster performance. The method includes receiving at least one state data point regarding power consumption or temperature of at least one resource within the compute environment. Using intelligent policies to control power consumption, the method implements and interfaces with power managements facilities within the cluster, grid or on-demand center to either implement policies, make dynamic changes, make predictions or actions, and so forth to reduce one or more of the direct or indirect power consumption associated with a compute environment. The method can analyze current workload, future workload or both in taking energy saving actions in the environment. An aspect can also involve reporting state information and updating algorithms based on historical experience or outside sources of information such as the news or weather.

System and method for managing energy consumption in a compute environment

A high-performance, superscalar-based computer system with out-of-order instruction execution for enhanced resource utilization and performance throughput. The computer system fetches a plurality of fixed length instructions with a specified, sequential program order (in-order). The computer system includes an instruction execution unit including a register file, a plurality of functional units, and an instruction control unit for examining the instructions and scheduling the instructions for out-of-order execution by the functional units. The register file includes a set of temporary data registers that are utilized by the instruction execution control unit to receive data results generated by the functional units. The data results of each executed instruction are stored in the temporary data registers until all prior instructions have been executed, thereby retiring the executed instruction in-order.

High performance, superscalar-based computer system with out-of-order instruction execution

A pipeline control system is distributed over the functional units (15, 17, 20, 25) in a processor (10). Decoder logic (12) issues operations, each with an associated tag, to the functional units, with up to n operations allowed to be outstanding. The units execute the operations and report termination information back to the decoder logic, but do not irrevocably change the state of the machine. Based on the termination information, the decoder logic retires normally terminated operations in order. If an operation terminates abnormally, the decoder logic instructs the units to back out of those operations that include and are later than the operation that terminated abnormally.

Processor having plurality of functional units for orderly retiring outstanding operations based upon its associated tags

To increase the performance of a pipelined processor executing various classes of instructions, the classes of instructions are executed by respective functional units(164-167) which are independently controlled and operated in parallel. The classes of instructions include integer instructions (164) floating point instructions (165), multiply instructions (166), and divide instructions (161). The integer unit, which also performs shift operations, is controlled by the microcode execution unit (26) to handle the wide variety of integer and shift operations included in a complex, variable-length instruction set. The other functional units need only accept a control command to initiate the operation to be performed by the functional unit. The retiring of the results of the instructions need not be controlled by the microcode execution unit, but instead is delegated to a separate retire unit (173) that services a result queue (172). When the microcode execution unit determines that a new operation is required, an entry is inserted into the result queue. The entry includes all the information needed by the retire unit to retire the result once the result is available from the respective functional unit. The retire unit services the result queue by reading a tag in the entry at the head of the queue to determine the functional unit that is to provide the result. Once the result is available and the destination specified by the entry is also available, the result is retired in accordance with the entry, and the entry is removed from the queue.

Method and apparatus for preprocessing multiple instructions in a pipeline processor

In a pipelined computer system, memory access functions are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical addresses resulting from the translation buffer 30 are passed to a cache 28 of the main memory 14 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.

Method and apparatus for ordering and queueing multiple memory access requests

A system control unit (SCU), adapted to operating a plurality of central processor units (CPUs) in a parallel fashion in combination with at least one input/output (I/O) unit and for allowing the CPUs and I/O units to controllably access address segments of a system memory, arbitrates communication requests received at the SCU ports from the CPUs and I/O units in such a manner that available system resources are optimally used, while at the same time guaranteeing that all requests are granted within a reasonable period of time. Incoming communication requests are stored, and from there these incoming communication requests are selected, on the basis of a pre-defined prioritizing scheme, commands corresponding to requests that are to be arbitrated. For the command corresponding to each request selected for being arbitrated, there is generated a first vector defining all system resources that are required for executing the command. A second vector is generated representative of all system resources that are in fact available at the time of arbitration. The first and second vectors are compared, and the selected command is honored if all corresponding required resources are available; otherwise, the request corresponding to the command is placed on reserved status, and the availability of corresponding required resources for the reserved request is rechecked, and the reserved request is subsequently honored by executing the associated command when corresponding reserved resources become available.

System for arbitrating communication requests using multi-pass control unit based on availability of system resources

An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source or destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system

In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is identified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

Tryggve Fossum

Papers

Method and apparatus for preprocessing multiple instructions in a pipeline processor

Method and apparatus for ordering and queueing multiple memory access requests

System for arbitrating communication requests using multi-pass control unit based on availability of system resources

Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system

Method and apparatus for detecting and correcting errors in a pipelined computer system