Both detection and tracking people are challenging problems, especially in complex real world scenes that commonly involve multi-person, complicated occlusions, and cluttered backgrounds. In this paper, we propose a novel approach for multi-person tracking-by-detection using deformable part models in Kalman filtering framework. The Kalman filter is used to keep track of each person and a unique label is assigned to each tracked individual. Based on this approach, people can enter and leave the scene at random. We test and demonstrate our results on the Caltech Pedestrian benchmark, which is the largest available dataset and consists of pedestrians varying widely in appearance, pose and scale. Complex situations such as people merging together are handled gracefully and individual persons can be tracked correctly after a group of people split. Experiments demonstrate the real-time performance and robustness of our system working in complex scenes. Our tracking model gives a tracking accuracy of 72.8% and a tracking precision of 82.3%.

Pedestrian detection and tracking using deformable part models and Kalman filtering

Non-binary low-density parity-check (NB-LDPC) codes are an extension of binary LDPC codes with significantly better performance when the code length is moderate. Previously, forward-backward schemes are used to implement check node processing, which need large memory. In this paper, a novel approach is proposed for EMS NB-LDPC decoding. Compared to EMS decoding algorithm, the message memory and the average number of iterations have been reduced. Also, the overall decoder architecture is proposed.

Efficient EMS decoding for non-binary LDPC codes

Compressive sensing (CS) as an approach for data acquisition has recently received much attention. In CS, the signal recovery problem from the observed data requires the solution of a sparse vector from an underdetermined system of equations. The underlying sparse signal recovery problem is quite general with many applications and is the focus of this talk. The main emphasis will be on Bayesian approaches for sparse signal recovery. We will examine sparse priors such as the super-Gaussian and student-t priors and appropriate MAP estimation methods. In particular, re-weighted l2 and re-weighted l1 methods developed to solve the optimization problem will be discussed. The talk will also examine a hierarchical Bayesian framework and then study in detail an empirical Bayesian method, the Sparse Bayesian Learning (SBL) method. If time permits, we will also discuss Bayesian methods for sparse recovery problems with structure; Intra-vector correlation in the context of the block sparse model and inter-vector correlation in the context of the multiple measurement vector problem.

Proceedings of the 35th WIC Symposium on Information Theory in the Benelux and the 4th joint WIC/IEEE Symposium on Information Theory and Signal Processing in the Benelux, Eindhoven, the Netherlands May 12-13, 2014

In an MMSE based turbo equalization system, a soft mapper calculates the symbol mean and variance based on extrinsic Log-Likelihood-Ratios (LLRs) information coming from a Soft-Input Soft-Output (SISO) decoder. In this paper, we investigate the complexity of this module, and in particular, we employ a 3-segment linear approximation approach to calculate the mean and variance of data symbols from LLRs. For FPGA and VLSI implementation, we propose novel piecewise linear functions which map LLR to the mean and variance directly without the use of any two-variable-input multipliers. Simulation results for 16-QAM and 64-QAM show that the no multiplier approach has close BER performance to the 3-segment linear approximation approach with multipliers.

/pdf/a-low-cost-soft-mapper-for-turbo-equalization-with-high-3k8zrdup80.pdf

A low cost soft mapper for turbo equalization with high order modulation

ACS (Add-Compare-Select) units are the most important block in FEC (Forward Error Correction) decoders such as Viterbi decoder and Turbo decoder. Due to the increase of performance requirement in next generation mobile communication systems such as LTE-Advanced, high speed operation of ACS units also becomes more important to achieve high throughput requirement. In this paper, we present three types of high-speed radix-4 ACS unit implementation for 12-bit operands and compare hardware complexities for various operating clock periods with 40% margin in 65nm CMOS process.

http://ieeexplore.ieee.org/iel7/6853539/6863951/06863958.pdf

High-speed radix-4 Add-Compare-Select unit for next generation communication systems

In this paper, we design and implement a high-throughput turbo decoder for the 3rd Generation Partnership Project (3GPP) Long Term Evolution-Advanced (LTE-advanced) system. To support the high data rate, we adopts eight radix-4 parallel soft-in/soft-output decoders. The properties of quadratic permutation polynomial (QPP) interleaver are exploited, and a new interconnection network is designed with simple rotator and control logic. The storages and arithmetic units related with branch metric are saved by taking advantage of the odd symmetry of all the possible combinations. A re-timing technique is also used to cut down the critical path delay, especially in the recursive radix-4 address generator. From synthesis result, this work can operate at 405 MHz to offer decoding data rate up to 510 Mbps in 90nm CMOS technology.

Tsao-Shuan Lee

Papers

High-throughput turbo decoder design with new interconnection network for LTE/LTE-A system