A system and method in a building or vehicle for an actuator operation in response to a sensor according to a control logic, the system comprising a router or a gateway communicating with a device associated with the sensor and a device associated with the actuator over in-building or in-vehicle networks, and an external Internet-connected control server associated with the control logic implementing a PID closed linear control loop and communicating with the router over external network for controlling the in-building or in-vehicle phenomenon. The sensor may be a microphone or a camera, and the system may include voice or image processing as part of the control logic. A redundancy is used by using multiple sensors or actuators, or by using multiple data paths over the building or vehicle internal or external communication. The networks may be wired or wireless, and may be BAN, PAN, LAN, WAN, or home networks.

System and method for server based control

Sensing systems such as biomedical implants, infrastructure monitoring systems, and military surveillance units are constrained to consume only picowatts to nanowatts in standby and active mode, respectively. This tight power budget places ultra-low power demands on all building blocks in the systems. This work proposes a voltage reference for use in such ultra-low power systems, referred to as the 2T voltage reference, which has been demonstrated in silicon across three CMOS technologies. Prototype chips in 0.13 μm show a temperature coefficient of 16.9 ppm/°C (best) and line sensitivity of 0.033%/V, while consuming 2.22 pW in 1350 μm2. The lowest functional Vdd 0.5 V. The proposed design improves energy efficiency by 2 to 3 orders of magnitude while exhibiting better line sensitivity and temperature coefficient in less area, compared to other nanowatt voltage references. For process spread analysis, 49 dies are measured across two runs, showing the design exhibits comparable spreads in TC and output voltage to existing voltage references in the literature. Digital trimming is demonstrated, and assisted one temperature point digital trimming, guided by initial samples with two temperature point trimming, enables TC <; 50 ppm/°C and ±0.35% output precision across all 25 dies. Ease of technology portability is demonstrated with silicon measurement results in 65 nm, 0.13 μm, and 0.18 μm CMOS technologies.

A Portable 2-Transistor Picowatt Temperature-Compensated Voltage Reference Operating at 0.5 V

A solid-state imaging apparatus which performs a global exposure operation, in a determined imaging region, for performing exposure as matching respective start times and respective end times of all rows, comprises: plural unit pixels arranged in two-dimensional matrix and each comprising a photoelectric converting unit for generating a pixel signal by photoelectric conversion, a holding unit for holding the generated pixel signal, and a first gate for transferring the generated pixel signal to the holding unit; a first controlling line connected commonly to the first gates in the unit pixels on the same row; a vertical controlling circuit for resetting the unit pixel; and a first driving line connected to the first controlling line, and not connected to and thus independent of the vertical controlling circuit, thereby enabling to reduce a current flowing in a power supply of the vertical controlling circuit when driving electrodes of the holding units.

Solid-state imaging apparatus

A solid-state imaging apparatus includes a pixel array in which a plurality of pixels are arranged, wherein the pixel array has a region formed from one of an electrical conductor and a semiconductor to which a fixed electric potential is supplied, each pixel includes a photoelectric converter, a charge-voltage converter which converts charges generated by the photoelectric converter into a voltage, and an amplification unit which amplifies a signal generated by the charge-voltage converter by a positive gain and outputs the amplified signal to an output line, and the output line comprising a shielding portion arranged to shield at least part of the charge-voltage converter with respect to the region

Solid-state imaging apparatus and imaging system

The invention includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. Embedding the stacked open pattern inductor in a magnetic oxide or in an insulator and a magnetic material increases the inductance of the inductor and allows the magnetic flux to be confined to the area of the inductor. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

Open pattern inductor

An active pixel sensor including low threshold voltage transistors advantageously provides an increased output swing over an active pixel sensor of the prior art. The low threshold voltage transistor can be achieved using either a native transistor or a depletion mode transistor. In a process in which a threshold adjustment implant step is separately masked, the active pixel sensor of the present invention can be manufactured with no additional masking requirements. In one embodiment, a low threshold voltage (VTN) allows a transistor acting as a reset switch to operate in the linear region, and allowing the reset switch transistor to share a common supply voltage source with a readout amplifier transistor.

CMOS active pixel sensor using native transistors

The high Q inductor process for reducing substrate interaction of integrated inductors includes etching away some of the silicon substrate after the inductor has been formed on the substrate. A first etch process is performed to form an opening in the center of the inductor exposing the silicon substrate. A second etch process is performed to etch the exposed silicon substrate to form a trench in the silicon substrate. A third etch process is performed to etch the trench into an inverted pyramidal cavity within the substrate and extending beneath the inductor. The pyramidal cavity is then filled with a solution, such as spin-on-glass thereby providing mechanical support for the inductor.

Tsung-Wen Lee

Papers

CMOS active pixel sensor using native transistors

Integrated inductor with filled etch