T
Tuo-Hsin Chien
Researcher at Fairchild Semiconductor International, Inc.
Publications - 20
Citations - 214
Tuo-Hsin Chien is an academic researcher from Fairchild Semiconductor International, Inc.. The author has contributed to research in topics: Breakdown voltage & Field-effect transistor. The author has an hindex of 8, co-authored 20 publications receiving 214 citations.
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Patent
Isolated high-voltage LDMOS transistor having a split well structure
TL;DR: The isolated highvoltage LDMOS transistor according to the present invention includes a split N-well and P-well in the extended drain region, which deplete the drift region and shifts the electric field maximum into the bulk of the Nwell as discussed by the authors.
Patent
High voltage ldmos transistor having an isolated structure
TL;DR: In this paper, a high voltage LDMOS transistor with a P-field and divided P-fields in an extended drain region of a N-well is presented. But, the Pfield is not used in this paper.
Patent
High voltage and low on-resistance ldmos transistor having equalized capacitance
TL;DR: In this paper, the P-field blocks form the junction fields in the N-well for equalizing the capacitance of parasitic capacitors between the drain region and the source region and fully deplete the drift region before breakdown.
Patent
Electrostatic discharge protection semiconductor structure
TL;DR: In this paper, an electrostatic discharge (ESD) protection device with adjustable single-trigger or multi-trigger voltage is provided, which can meet the requirements of high power semiconductor device and has better protection function compared to conventional ESD protection circuit.
Patent
Vertical transistor with field region structure
TL;DR: In this paper, a structure of a vertical transistor with a field-doping region formed in a substrate next to a core region of the vertical transistor is provided. And the field region is connected to respective well of rim core regions of vertical transistor to realize a stable breakdown voltage.