Modern electronics testing has a legacy of more than 40 years. The introduction of new technologies, especially nanometer technologies with 90nm or smaller geometry, has allowed the semiconductor industry to keep pace with the increased performance-capacity demands from consumers. As a result, semiconductor test costs have been growing steadily and typically amount to 40% of today's overall product cost. 

This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and VLSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.

KEY FEATURES
* Emphasizes VLSI Test principles and Design for Testability architectures, with numerous illustrations/examples.
* Most up-to-date coverage available, including Fault Tolerance, Low-Power Testing, Defect and Error Tolerance, Network-on-Chip (NOC) Testing, Software-Based Self-Testing, FPGA Testing, MEMS Testing, and System-In-Package (SIP) Testing, which are not yet available in any testing book.
* Covers the entire spectrum of VLSI testing and DFT architectures, from digital and analog, to memory circuits, and fault diagnosis and self-repair from digital to memory circuits.
* Discusses future nanotechnology test trends and challenges facing the nanometer design era; promising nanotechnology test techniques, including Quantum-Dots, Cellular Automata, Carbon-Nanotubes, and Hybrid Semiconductor/Nanowire/Molecular Computing.
* Practical problems at the end of each chapter for students.

System-on-Chip Test Architectures: Nanometer Design for Testability

Precise failure analysis requires accurate fault diagnosis. A previously proposed method for diagnosing bridging faults using single stuck-at dictionaries was applied only to small circuits, produced large and imprecise diagnoses, and did not take into account the Byzantine Generals Problem for bridging faults. We analyze the original technique and improve it by introducing the concepts of match restriction, match requirement, and failure recovery. Our new technique, which requires no information other than that used by standard stuck-at methods, produces diagnoses that are an order of magnitude smaller than those produced by the original technique and produces many fewer misleading diagnoses than that of traditional stuck-at diagnosis.

Diagnosis of realistic bridging faults with single stuck-at information

The programmable cores on SoCs can perform on-chip test generation, measurement, response analysis, and even diagnosis. This software-based approach to self-testing enables at-speed testing and incurs low DFT overhead. We give an overview of the existing embedded software-based self-testing and self-diagnosis methods for core-based SoC designs, and we discuss the challenges to further developing this new testing paradigm.

Embedded software-based self-test for programmable core-based designs

Physical defects cause behaviors unmodeled by even the best fault simulators, which complicates predictive diagnosis. This paper reports on a diagnosis procedure that uses modified composite signatures constructed from single stuck-at information combined with a lexicographic matching and ranking algorithm. The diagnosis procedure is used to perform high-quality bridging fault diagnosis for more than 400,000 diagnostic experiments involving dropping or adding behaviors from the simulations of faulty circuits.

Beyond the byzantine generals: unexpected behavior and bridging fault diagnosis

Fault equivalence is an essential concept in digital design with significance in fault diagnosis, diagnostic test generation, testability analysis and logic synthesis. In this paper, an efficient algorithm to check whether two faults are equivalent is presented. If they are not equivalent, the algorithm returns a test vector that distinguishes them. The proposed approach is complete since for every pair of faults it either proves equivalence or it returns a distinguishing vector. This is performed with a simple hardware construction and a sequence of simulation/ATPG-based steps. Experiments on benchmark circuits demonstrate the competitiveness of the proposed method.

Fault equivalence and diagnostic test generation using ATPG

The authors present an efficient algorithm for the generation of diagnostic test patterns which distinguish between two arbitrary single stuck-at faults. The algorithm is able to extend a given set of test patterns which is generated from the viewpoint of fault detection to a diagnostic test pattern set with a diagnostic resolution down to a fault equivalence class. The difficult problem of identifying the equivalence of two faults, analogous to the problem of redundancy identification in ATPG, has been solved. The efficiency of the algorithm is demonstrated by experimental results for a set of benchmark circuits. DIATEST, the implementation of the algorithm, either generates diagnostic test patterns for all distinguishable pairs of faults or identifies pairs of faults as being equivalent for each of the benchmark circuits. >

U. Mahlstedt

Papers

DIATEST: a fast diagnostic test pattern generator for combinational circuits