Anisotropic etching of silicon has become an important technology in silicon semiconductor processing during the past ten years. It will continue to gain stature and acceptance as standard processing technology in the next few years. Anisotropic etching of

Anisotropic etching of silicon

Thermal bonding of oxidized silicon wafers is used to obtain high-quality silicon on insulator (SOI) starting material for electronics and sensor applications. An overview of the technology is followed by a detailed description of the bonding technique and the ensuing wafer thinning processes for making SOI of various film thicknesses. Bonded pairs of wafers can be reproducibly produced free of contact voids. Thick-film SOI is produced using a simple bond and grind/polish technique. Thin-film SOI, suitable for CMOS applications, is produced using the bond and etch back (BE-SOI) process. A comparison of selective etch-back chemistry with different etchstop fabrication techniques is presented. These methods produce inexpensive, low-defect SOI, for integrated circuit applications, using materials and equipment common to silicon integrated circuit process lines.

Silicon on insulator material by wafer bonding

Single‐crystal silicon films have been grown over SiO2‐covered regions of a single‐crystal silicon wafer by lateral epitaxial chemical vapor deposition (CVD). Nucleation of polycrystalline silicon on the SiO2 is suppressed by adding HCl to the SiH4 deposition gas. Sequential variation of the HCl partial pressure during different stages of the deposition process controls the relative deposition rates of the [100] and [110] planes and, consequently, the shape of the laterally advancing growth fronts, allowing the fronts from opposite sides of the SiO2 region to join uniformly. A plane surface is obtained by increasing the HCl partial pressure after coalescence. A standard silicon CVD epitaxial reactor is used for the deposition.

Control of lateral epitaxial chemical vapor deposition of silicon over insulators

The double-polysilicon self-aligned bipolar device structure has come a long way since its first inception, but there is still room for further scaling of this structure and continued improvements in performance. An analysis of the current state-of-the-art double-poly structure leads naturally to a discussion of future trends and technologies necessary to continue scaling into the sub-0.25 /spl mu/m regime. In addition, it has become highly desirable to extend bipolar processes in new directions to take advantage of the opportunities offered by emerging materials technologies, such as bonded silicon-on-insulator films and medium or low temperature Si and SiGe epitaxy. Opportunities also exist for high-performance bipolars in BiCMOS technology and in complementary bipolar processes for low-power, high-speed digital applications. These extensions beyond "conventional" bipolar technology will be discussed in terms of their requirements and the device structures that are evolving to match these needs. >

Silicon bipolar device structures for digital applications: technology trends and future directions

A study was made of the factors affecting the reliability of large-scale integrated (LSI) circuits. Particular attention was given to the effect on array reliability of the additional processing steps required to obtain multilevel metalization. The additional significant steps are low temperature deposition of a second dielectric layer on metalized LSI wafers, etching of vias through the second dielectric, and second level metalization. Consideration was also given to the effect of other trends in LSI, such as the use of smaller geometry and closer spacings. Possible new failure modes in multilevel arrays are: 1) shorts or increased leakage through or along deposited second layer dielectrics, 2) opens or increased series resistance in conductors, and 3) silicon surface effects. A review of literature on LSI was supplemented by results of a number of concurrent LSI programs and experimental studies. Test vehicles were designed to provide fundamental information about each of the categories of failure. Data obtained using these test vehicles to evaluate the multilevel metalized array structures are presented. A discussion concerning the merits and limitations of the specially designed test vehicles for process development, process control, and reliability tests is given. It is concluded that with the proper in-process controls, tests and screens, LSI arrays will be substantially more reliable per function accomplished than are conventional integrated circuits.

Failure mechanisms in large-scale integrated circuits

Dielectric isolation has proven effective in raising inter-device breakdown voltages, lowering parasitic capacitances, and increasing resistance to radiation damage. The fabrication of a dielectric-isolated substrate, prior to diffusions, requires adequate control of the thickness of the epitaxial layer, of crowning and warpage, and of a necessarily smooth, damage-free surface. The mere juxtaposition of three or more layers of different materials, even before diffusion-induced strains, creates special problems because of coefficient-of-expansion mismatches. In addition, the substrates must pass through subsequent diffusion cycles and permit the fabrication of transistors with characteristics as good as (or better than) those made on p-n junction isolated substrates. There are three major methods of using silicon dioxide as a dielectric to separate active areas of an integrated circuit: 1) shape-back to the channels of a wafer which has had channels etched out and filled with polycrystalline silicon; 2) etch out and fill in with single crystal on an n+wafer which has already had isolation moats created; and 3) growth of polycrystalline silicon prior to etching the isolating channels. This paper describes and compares these methods.

U.S. Davidsohn

Papers

Dielectric isolated integrated circuit substrate processes