Efficient memory-based VLSI arrays and a new design approach for the discrete Fourier transform (DFT) and discrete cosine transform (DCT) are presented. The DFT and DCT are formulated as cyclic convolution forms and mapped into linear arrays which characterize small numbers of I/O channels and low I/O bandwidth. Since the multipliers consume much hardware area, the designs utilize small ROMs and adders to implement the multiplications. Moreover, the ROM size can be reduced effectively by arranging the data in the designs appropriately. The arrays outperform others in the architectural topology (local and regular connection), computing speeds, hardware complexity, the number of I/O channels, and I/O bandwidth. They benefit from the advantages of both systolic array and the memory-based architectures. >

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The efficient memory-based VLSI array designs for DFT and DCT

A new approach to derive a systolic algorithm for primelength discrete cosine transform (DCT) is proposed. It makes use of the input/output (UO) data permutations and the symmetry property of cosine kernels such that the proposed array possesses outstanding E ( i A ) * = B,?. (4.2) performance in hardware cost of the processing elements (PE’s), average computation time, and the I/O cost. the asymptotic variances

https://ir.nctu.edu.tw:443/bitstream/11536/3159/1/A1993KG14800046.pdf

A New Array Architecture for Prime-Length Discrete Cosine Transform

An efficient MPEG-2 video decoder architecture together with several effective bus-arbitration schemes designed to meet the main profile at main level (MP@ML) real-time decoding requirement is presented. The overall architecture, as well as the design of major function-specific processing blocks (variable-length decoder, inverse two-dimensional discrete cosine transform unit, and motion-compensation unit), is discussed. A hierarchical and distributed controller approach is used, a bus-monitoring model for different bus-arbitration schemes to control external DRAM accesses is developed, and the system is simulated. Practical issues and buffer sizes are addressed and evaluated. With a 27 MHz clock, our architecture uses many fewer than the 667 cycles, the upper bound for the MP@ML decoding requirement, to decode each macroblock with a single external bus and DRAM.

Architecture and bus-arbitration schemes for MPEG-2 video decoder

In this paper, a new approach for the realization of 1D discrete cosine transform (1D-DCT) is presented. This approach is based on a new formulation of an odd prime-length DCT which uses two half-length cyclic convolutions with the same form which can be computed in parallel. Using this approach, a new efficient systolic array with outstanding performance in structural regularity, hardware cost of the PE's, average computation time, and I/O cost has been obtained, which is well suited for VLSI realization. The average computation time has been reduced to one half and the throughput has been doubled, as compared with a previous design. It possesses also a much lower control complexity, a simpler interconnection structure, and a simpler hardware structure of the PE's, having thus a shorter cycle time. Moreover, it owns all other outstanding features of the systolic array previously proposed.

http://ieeexplore.ieee.org/iel3/3834/11196/00541833.pdf

Novel systolic array design for discrete cosine transform with high throughput rate

In this paper, we propose an efficient two-dimensional inverse discrete cosine transform (2-D IDCT) algorithm based upon coefficient-by-coefficient implementations. The algorithm, which is developed in the use of the symmetrical properties of computational kernel matrices, can effectively combine with the run length code (RLC) decoder in progressive manners. The proposed method requires only N/2 multipliers in an 'N/spl times/N' 2-D IDCT processor. By evaluating the efficiency performance, the processor can complete 2N/M pixels per multiplier per system cycle where M is the number of non-zero quantized DCT coefficients. Due to its inherent parallel and coefficient-by-coefficient characteristics, the proposed efficient 2-D IDCT algorithm is suitable for the future digital HDTV receivers and recording systems. >

U. Totzek

Papers

Two-dimensional discrete cosine transform with linear systolic arrays