The author examines the effect of the stage resolution on some important characteristics of monolithic, pipelined, multistage, analog-to-digital converters (ADCs) with identical stages for video-rate applications. These characteristics are the linearity, speed, area, and power dissipation. It is found that although large stage resolution is desirable from a linearity standpoint, the effect of stage resolution on linearity is small if the ADC uses redundancy and digital correction and if the magnitude of the interstage gain is at least two. Also, minimizing the stage resolution maximizes the conversion rate and minimizes both the die area and the power dissipation. >

Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications

A two-step recycling technique is applied to implement a 10-b CMOS analog-to-digital (A/D) converter with a video conversion rate of 15 Msample/s. In a prototype digitally corrected converter, one capacitor-array multiplying digital-to-analog converter (MDAC) is used repeatedly as a sample-and-hold (S/H) amplifier, a DAC, and a residue amplifier so that the proposed converter may obtain linearity with the capacitor-array matching. An experimental fully differential A/D converter implemented using a double-poly 1- mu m CMOS technology consumes 250 mW with a 5-V single supply, and its active die area, including all digital logic and output buffers, is 1.75 mm/sup 2/ (2700 mil/sup 2/). Because the conversion accuracy of the proposed architecture relies on a capacitor-array MDAC linearity, high-resolution CMOS A/D conversions are feasible at high frequencies if sophisticated circuit techniques are further developed. For high-speed two-phase versions, the system can be easily modified to use multiplexing and/or pipelining techniques with a separate S/H amplifier and/or two separate flash converters. >

A 10-b 15-MHz CMOS recycling two-step A/D converter

A 10-b, 5Msample/s, two-step flash A/D converter fabricated in a 1.6 mu m CMOS process is described. The architecture is based on a resistor string and capacitor arrays and was developed to overcome the disadvantages of the previous approaches, namely flash, pipelined, and classical two-step converters. With minimal capacitor matching requirements and comparator offset voltage cancellation, the converter is monotonic. To minimize charge-injection errors the converter is fully differential. A high-speed comparator architecture using three comparator stages was designed to provide a gain of more than 1000, and a comparison time of less than 10 ns. The total area of the converter excluding the bonding pads is 54 kmil/sup 2/. Power dissipation is 350 mW, of which 60 mW is dissipated in the resistor string. >

A 10-bit 5-Msample/s CMOS two-step flash ADC

A CMOS subranging analog-to-digital converter (ADC) incorporates several features to enhance performance and reduce power dissipation. The combination of an extended settling period for the fine references, absolute-value signal processing, and interpolation in the comparator banks alleviates the principal speed-limiting operation. A front-end sample-and-hold amplifier (SHA) provides sustained dynamic performance at high input frequencies and performs single-ended to differential conversion with a signal gain of two and with low distortion. The SHA holds its differential output for a full clock cycle while it simultaneously samples the next single-ended input, thereby allowing it to drive two comparator banks on consecutive clock phases. The remaining analog circuits are implemented in a fully differential manner. The use of pipelining allows every input sample to be processed by the same channel, thereby avoiding the use of ping-pong techniques, while providing a conversion latency of only two clock cycles. The dynamic performance with a single-ended input approaches that of an ideal ill-bit ADC, typically providing 9.7 effective bits for low input frequencies and 9.5 bits at Nyquist. This performance level is comparable to the best reported for 10-bit CMOS ADC's with differential inputs and significantly better than those with single-ended inputs. The typical maximum differential nonlinearity is /spl plusmn/0.4 LSB, and the maximum integral nonlinearity is /spl plusmn/0.55 LSB without trimming or calibration. With an ADC power of 55 mW plus an SHA power of 20 mW from a 5-V supply, the active area is 1.6 mm/sup 2/ in a 0.5-/spl mu/m double-poly, double-metal CMOS technology.

A 75-mW, 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist

The design of a fully differential BiCMOS comparator suitable for application in data conversion, instrumentation, and communication systems operating at video frequencies and above is discussed. By exploiting the advantages presented by the integration of both bipolar and CMOS devices within the same technology, the comparator dissipates less power than conventional bipolar designs without sacrificing operating speed. The comparator includes an input stage that combines MOS sampling with a bipolar regenerative amplifier. This stage dissipates no static power and, because the amplification is provided by a bipolar differential pair, no offset cancellation is needed to achieve 8-b precision. Furthermore, the need for preamplification and the attendant power-delay penalty associated with preamplifier overdrive recovery are avoided. An experimental version of the comparator, consisting of the BiCMOS regenerative input stage followed by a current-switched latch, has been integrated in a 0.8- mu m BiCMOS technology with an area of 140*75 mu m. This circuit performs comparisons to a precision of 8 b at rates up to 200 MHz. The entire circuit dissipates only 1.6 mW at the maximum clock rate while operating from a single 5-V supply. >

An 8-bit 200-MHz BiCMOS comparator

An 8b 20mhz Cmos Half-Flash A/D Converter

http://ieeexplore.ieee.org/iel5/8048/22245/01037488.pdf

Ueda

Papers

An 8b 20mhz Cmos Half-Flash A/D Converter

An 8 bit 100 MHz 3 channel CMOS DAC with analog switching current cells