Showing papers by "Ulrich Rückert published in 1993"

Hardware Design for Self-Organizing Feature Maps with Binary Input Vectors

Abstract: A number of applications of self organizing feature maps require a powerful hardware. The algorithm of SOFMs contains multiplications, which need a large chip area for fast implementation in hardware. In this paper a resticted class of self organizing feature maps is investigated. Hardware aspects are the fundamental ideas for the restictions, so that the necessary chip area for each processor element in the map can be much smaller then before and more elements per chip can work in parallel. Binary input vectors, Manhatten Distance and a special treatment of the adaptation factor allow an efficient implementation. A hardware design using this algorithm is presented. VHDL simulations show a performance of 25600 MCPS (Million Connections Per Second) during the recall phase and 1500 MCUPS (Million Connections Updates Per Second) during the learning phase for a 50 by 50 map. A first standard cell layout containing 16 processor elements and full custom designs for the most important parts are presented.

Error coding data transmission method - recognising and/or correcting one and more bit errors and involves division of data word and test word into four bit wide part words

Abstract: The data recognition and correction method is provided for data words that are printable via data collection lines into memory units from which they can be read out. The data words are suspended in generator test words and in common with the data word are transmittable from a data transmitter. With a data receiver a syndrome word is producible from a difference formation of the actual test word and the theoretical test word. By corresp. control of a correction unit an error correction and a repetition of the printing/read process brought about. A number of p EX-OR trees (100, 101) are provided, which with reference to a data word length provided with test words has a number of d/4 inputs X, which are fed from d/4 searched bits of the data word, and lies at the outlet (18) as evidence of one of a number p test bits, so that in all through the number p EX-OR trees (100, 101) the total p test bits of the test word can be produced. USE/ADVANTAGE - In data transmission, to optimise error recognition and error corrections possibilities, minimising the coding depth and thereby the number of necessary grid planes.

Method and device for error coding data transmission

Abstract: The invention relates to a method and a device for detection and / or correction of 1- and multiple-bit errors according to the preamble of claims 1 and 5. In order, in a method and a device of the generic type, an optimization of error detection and error correction while minimizing to reach the coding depth ie the number of necessary gate planes is, the invention proposes to divide the data word and the check word in each 4-bit wide part words, the check word of a number of p check bits and the data word is formed of a plurality of d data bits , For Prufwortgenerierung a d * p generator matrix is ​​used, wherein each column vector comprises generating weight Gs = d / 4, and each row vector is the generation weight Gz = p / 4, so that line by line, each data bit affects a maximum of 2 bits in a Prufteilwort.