The recently uncovered problem of multi-point progressive blocking (MPB) has significantly increased the complexity of schedulability analysis of priority-preemptive wormhole networks-on-chip. While state-of-the-art analysis is currently deemed safe, there is still significant inherent pessimism when it comes to considering backpressure issues caused by downstream indirect interference. In this paper, we attempt to simplify the problem by considering a novel flow control protocol that can avoid backpressure issues, enabling simpler schedulability analysis approaches to be used. Rather than construct the analysis to fit the protocol, we modify the protocol so that effective analysis applies. We describe the changes to a baseline wormhole router in order to implement the proposed protocol, and comment on the impact on hardware overheads. We also examine the number of routers that actually require these changes. Comparative analysis of FPGA implementations show that the hardware overheads of the proposed NoC router are comparable or lower than those of the baseline, while analytical comparison shows that the proposed approach can guarantee schedulability in up to 77% more cases.

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A Novel Flow Control Mechanism to Avoid Multi-Point Progressive Blocking in Hard Real-Time Priority-Preemptive NoCs

Network on chip NOC platform for high performance computing

This paper presents a heterogeneous adaptable router to reduce latency in irregular mesh Network-on-Chip (NoC) architectures. Regular mesh-based NoC architecture may become irregular due to variable sized IPs and needs new routing algorithms to ensure throughput. Therefore, an irregular NoC mesh is considered and an adaptive algorithm is used for routing. The performance measures such as throughput, latency, and bandwidth are defined at design time to guarantee the performance of NoC. However, if the application has to change its communication pattern, parameters set at design time (say buffer size) may result in large area and power consumption or increased latency. Routers with large input buffers improve the efficiency of NoC communication, but they incur excessive power dissipation and hardware overheads. Routers with small buffers reduce power consumption, but result in high latency. In the proposed NoC router, input buffers can be dynamically allocated, thereby, latency can be reduced. In a 4 × 4 irregular mesh NoC with a buffer depth of 4 slots, 20% reduction in latency and 9% increase in throughput are attained using dynamic buffer allocation. An 8 × 8 irregular mesh NoC with the proposed router is exposed to the synthetic traffics like uniform, bit complement, tornado and hotspot traffics and it offered a 30.42% reduction in overall average latency and 18.33% increase in overall saturation throughput. The proposed router outperformed the static router by 22.63% less average latency for E3S benchmark applications. For the same performance, maximum of 55% reduction in buffer requirement and 53% less power consumption is achieved.

Umamaheswari S

Papers

Runtime buffer management to improve the performance in irregular Network-on-Chip architecture