In this paper, we propose a set of rules for consistent estimation of the real performance and power features of the flip-flop and master-slave latch structures. A new simulation and optimization approach is presented, targeting both high-performance and power budget issues. The analysis approach reveals the sources of performance and power-consumption bottlenecks in different design styles. Certain misleading parameters have been properly modified and weighted to reflect the real properties of the compared structures. Furthermore, the results of the comparison of representative master-slave latches and flip-flops illustrate the advantages of our approach and the suitability of different design styles for high-performance and low-power applications.

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Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems

Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occupy a large portion of the chip area. Not surprisingly, these caches often consume a significant amount of power. In many applications, such as portable devices, low power is more important than performance. We propose to trade performance for power consumption by filtering cache references through an unusually small L1 cache. An L2 cache, which is similar in size and structure to a typical L1 cache, is positioned behind the filter cache and serves to reduce the performance loss. Experimental results across a wide range of embedded applications show that the filter cache results in improved memory system energy efficiency. For example, a direct mapped 256-byte filter cache achieves a 58% power reduction while reducing performance by 21%, corresponding to a 51% reduction in the energy-delay product over conventional design.

The filter cache: an energy efficient memory structure

This paper proposes a new approach using way prediction for achieving high performance and low energy consumption of set-associative caches. By accessing only a single cache way predicted, instead of accessing all the ways in a set, the energy consumption can be reduced. This paper shows that the way-predicting set-associative cache improves the ED (energy-delay) product by 60-70% compared to a conventional set-associative cache,.

Way-predicting set-associative cache for high performance and low energy consumption

Modern microprocessors employ one or two levels of on-chip caches to bridge the burgeoning speed disparities between the processor and the RAM. These SRAM caches are a major source of power dissipation. We investigate architectural techniques, that do not compromise the processor cycle time, for reducing the power dissipation within the on-chip cache hierarchy in superscalar microprocessors. We use a detailed register-level simulator of a superscalar microprocessor that simulates the execution of the SPEC benchmarks and SPICE measurements for the actual layout of a 0.5 micron, 4-metal layer cache, optimized for a 300 MHz, clock. We show that a combination of subbanking, multiple line buffers and bit-line segmentation can reduce the on-chip cache power dissipation by as much as 75% in a technology-independent manner.

/pdf/reducing-power-in-superscalar-processor-caches-using-9xbob1l3pd.pdf

Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation

This paper is an in-depth review on silicon implementations of threshold logic gates that covers several decades. In this paper, we will mention early MOS threshold logic solutions and detail numerous very-large-scale integration (VLSI) implementations including capacitive (switched capacitor and floating gate with their variations), conductance/current (pseudo-nMOS and output-wired-inverters, including a plethora of solutions evolved from them), as well as many differential solutions. At the end, we will briefly mention other implementations, e.g., based on negative resistance devices and on single electron technologies.

/pdf/vlsi-implementations-of-threshold-logic-a-comprehensive-vqkiwr19v2.pdf

VLSI implementations of threshold logic-a comprehensive survey

To optimize performance and power of a processor’s cache, a multiple-divided module (MDM) cache architecture is proposed to save power at memory peripherals as well as the bit array. For a MxB-divided MDM cache, latency is equivalent to that of the smallest module and power consumption is only 1/MxB of the regular, non-divided cache. Based on the architecture and given transistor budgets for onchip processor caches, this paper extends investigation to analyze energy effects from cache parameters in a multi-level cache design. The analysis is based on execution of SPECint92 benchmark programs with miss ratios of a RISC processor.

Energy optimization of multi-level processor cache architectures

This invention involves logic circuits formed of metal oxide semiconductor field effect transistors having differing threshold voltages. In a first embodiment, the logic circuit includes a first and a second series connection. The first series connection between a first supply voltage and an output node consists of a source-drain path of an N-channel transistor having a high threshold voltage and a pull-down conditional conduction path of a pull-down network constructed exclusively of transistors having a low threshold voltage. The second series connection between said supply voltage and said output node consists of a source-drain path of a P-channel transistor having the high threshold voltage and a pull-up conditional conduction path of a pull-up network constructed exclusively of transistors having the low threshold voltage. The two high threshold voltage MOSFETs receive at their respective gates inverse signals so that either both are conducting or both are off. The pull-down network and pull-up network each receives input signals which control whether they conduct. These input signals are preferably selected so that the pull-down network and pull-up network do not conduct simultaneously. The two parts of each series connection may be in either order. The first input signal is preferably a clock signal. The pull-down network is preferably constructed exclusively of N-channel transistors. The pull-up network is preferably constructed exclusively of P-channel transistors.

Family of logic circuits emploting mosfets of differing thershold voltages

A D flip-flop circuit has two current paths supply the output signal of this flip-flop. A push-pull circuit including an inverter and a transmission gate clocked in a first phase supplies the output of the D flip-flop in a first output path. A slave latch connected to the transmission gate having an output clocked in a second phase opposite to the first phase serves as the second path to the output. In one alternative embodiment the master latch includes a transmission gate clocked in the second phase serving as input and a pair of cross coupled inverters serving as latch. The master latch may include a feedback P-type MOSFET. The slave latch may includes two slave latch inverters and a transmission gate clocked in the second phase connected to the output of the D flip-flop output. In a second alternative, an appropriately clocked tri-state inverter replaces the second slave latch inverter and the transmission gate. The master latch and the push-pull circuit may be combined and include two inverters, two transmission gates and a feedback P-type MOSFET. In a third embodiment the push-pull circuit consists of an appropriately clocked tri-state inverter.

Split-slave dual-path D flip flop

This paper investigates delay, power and area of critical components in designing energy-efficient control logic. To improve performance and energy efficiency, a split-slave dual-path (SSDP) register is proposed which improves the energy efficiency of the prior art by 30%. For multiplexers (MUX) three MUXes are proposed and compared to existing solutions. The proposed MUXes improve performance by 50% or power by 22%. The impact of scaling supply voltage alone and scaling threshold voltage with supply voltage on delay and power is also examined.

/pdf/design-techniques-for-high-performance-energy-efficient-3cq8fhys3q.pdf

Design techniques for high performance, energy efficient control logic

This paper investigates delay, power and area of several critical library components for high-performance, low-power microprocessor designs. To improve performance of a 0.18-/spl mu/m technology at a supply voltage of 1.8 V, the proposed hybrid dual-V/sub t/ (HDVT) circuit architectures enhance speed of low-V/sub t/ by 21% while reducing leakage power dissipation of low-V/sub t/ by an order of magnitude for combinatorial logic. For sequential elements, a HDVT split-slave dual-path (HSSDP) and Push-Pull Isolation (HPPI) registers are proposed to improve 29-92% performance over an HDVT-conventional registers with 20-89% less energy consumption. For the datapath, a HDVT hierarchical, reduced-swing, dual-V/sub t/ logic (HHRSL) comparator is proposed to improve the delay of prior arts by up to 50%.

Uming Ko

Papers

Energy optimization of multi-level processor cache architectures

Family of logic circuits emploting mosfets of differing thershold voltages

Split-slave dual-path D flip flop

Design techniques for high performance, energy efficient control logic

Hybrid dual-threshold design techniques for high-performance processors with low-power features