Methods and systems for using block chain technology to verify transaction data are described herein. A computing platform may receive data about events related to transactions, personal or corporate information, supply chains, and other relevant information about a person or corporate entity. The event information may be received, aggregated, and processed to determine metadata about the person or corporate entity. The metadata may indicate, for example, a trustworthiness of the person or corporate entity for various purposes. Such event information and/or metadata may be stored as transactions in a block chain that may be accessible by counterparties to a potential transaction involving the person or corporate entity. The automated event processing computing platform may further use automated techniques to implement smart transactions between the person/entity and counterparty based on the trust metadata.

Automated Event Processing Computing Platform for Handling and Enriching Blockchain Data

Disclosed herein are techniques for maintaining a secure execution environment on a server. In one embodiment, the server includes a non-volatile memory storing firmware, a programmable security logic coupled to the non-volatile memory, an adapter device coupled to the programmable security logic, and a processor communicatively coupled to the non-volatile memory via the programmable security logic. The adapter device and/or the programmable security logic can verify the firmware in the non-volatile memory while holding the processor and/or a baseboard management controller (BMC) in power reset, release the processor and the BMC from reset to boot the processor and the BMC after the firmware is verified, and then disable communications between the processor and the BMC and deny at least some requests to write to the non-volatile memory by the processor or the BMC.

Secure execution environment on a server

Various embodiments are generally directed to an apparatus, method and other techniques to de determine a secure memory region for a transaction, the secure memory region associated with a security association context to perform one or more of an encryption/decryption operation and an authentication operation for the transaction, perform one or more of the encryption/decryption operation and the authentication operation for the transaction based on the security association context, and cause communication of the transaction.

Techniques to provide client-side security for storage of data in a network environment

Non-volatile Memory Express over Fabric (NVMeOF) using Volume Management Device (VMD) schemes and associated methods, systems and software. The schemes are implemented in a data center environment including compute resources in compute drawers and storage resources residing in pooled storage drawers that are communicatively couple via a fabric. Compute resources are composed as compute nodes or virtual machines/containers running on compute nodes to utilize remote storage devices in pooled storage drawers, while exposing the remote storage devices as local NVMe storage devices to software running on the compute nodes. This is facilitated by virtualizing the system's storage infrastructure through use of hardware-based components, firmware-based components, or a combination of hardware/firmware- and software-based components. The schemes support the use of remote NVMe storage devices using an NVMeOF protocol and/or use of non-NVMe storage devices using NVMe emulation.

Non-volatile memory express over fabric (NVMeOF) using volume management device

In an embodiment, a processor includes a hardware accelerator to receive a message to be processed using the cryptographic hash algorithm; store a plurality of digest words in a plurality of digest registers; perform a plurality of rounds of the cryptographic hash algorithm, where the plurality of rounds is divided into first and second sets of rounds; in each cycle of each round in the first set, use W bits from the first digest register for a first function and use N bits from the second digest register for a second function; in each cycle of each round in the second set, use W bits from the second digest register for the first function and use N bits from the first digest register for the second function. Other embodiments are described and claimed.

Hardware accelerator for cryptographic hash operations

Embodiments detailed herein describe a system comprising a manageability server to generate an encrypted sideband message having at least one command; a server including: a radio frequency identification (RFID) device, the RFID device to include storage to store at least one encrypted sideband message having at least one command, and a security circuit coupled to the RFID device, the security circuit to: retrieve at least one encrypted sideband message from the RFID device storage, decrypt the one encrypted sideband message, determine validity of the decrypted sideband message using information from the decrypted sideband message, and perform an action in response to the at least one command.

Systems, apparatuses, and methods for platform security

Encryption of a BIOS using a programmable logic device (PLD) is described. A PLD may include a static random-access memory area including programmable logic in a Lookup Table to receive a request to authenticate a basic input/output system (BIOS) executing on a processor coupled to the PLD. The PLD may calculate a hash value of a message associated with the BIOS using a Secure Hash Algorithm (SHA). The PLD may also include a random-access memory area including a first embedded random access memory block (EBR) to store a first portion of a 256-bit message digest associated with the message, a fifth portion of the 256-bit message digest, and second, third, fourth, sixth, seventh, and eighth EBRs to store second, third, fourth, sixth, seventh, and eighth portions of the 256-bit message digest, respectively.

Hardware accelerator for platform firmware integrity check

A system for securing electronic devices includes a storage device including a storage device controller processor, at least one non-transitory machine readable storage medium in firmware of the storage device communicatively coupled to the storage device controller processor, and a monitor application comprising computer-executable instructions on the medium. The instructions are readable by the storage device controller processor. The monitor application is configured to provision one or more read-only areas of the storage device, provision a candidate copy area of the storage device, reduce a maximum capacity available for user data on the storage device by a size of the read-only areas and the candidate copy area, and secure access to the read-only areas of the storage device.

Remote provisioning and authenticated writes to secure storage devices

A processor can be configured to access boot firmware from a remote location independent from use of a chipset. After a processor powers-on or reboots, the processor can execute microcode. The microcode will cause the processor to train a link with a remote device. The remote device can provide the processor with access to boot firmware. The processor can copy the boot firmware to the processor's cache or memory. The processor will attempt to authenticate the boot firmware. If the boot firmware is authenticated, the processor executes the copy of the boot firmware.

Techniques for processor boot-up

In one embodiment, a processor includes: a first die including at least one processor core to execute instructions and a non-volatile storage to store an identifier to be provisioned into the processor during manufacture; a second die to couple to the first die, the second die including a wireless circuit and a second non-volatile storage; and a wireless interface to couple to the second die to enable wireless communication with a wireless device. The processor may be disabled if the identifier is not stored in the second non-volatile storage. Other embodiments are described and claimed.

Upasani Neeraj S

Papers

Systems, apparatuses, and methods for platform security

Hardware accelerator for platform firmware integrity check

Remote provisioning and authenticated writes to secure storage devices

Techniques for processor boot-up

System, Apparatus And Method For Securely Protecting A Processor In Transit