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Showing papers by "Uwe Meyer-Baese published in 1995"

Proceedings Article•DOI•
Realization of a neuronal hardware with digital signal processor and programmable gate arrays

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Anke Meyer-Baese1, Uwe Meyer-Baese1, Henning Scheich•
Darmstadt University of Applied Sciences1
06 Apr 1995
TL;DR: This paper describes how the processing speed of a radial basis neural network can be performed by the use of field programmable gate arrays (FPGA) and determines the number of FPGAs and does a processing speed comparison between FPGA and DSP referring to an application in speech recognition.
Abstract: In this paper we describe how the processing speed of a radial basis neural network can be performed by the use of field programmable gate arrays (FPGA). The calculation of the very time-consuming exponential function is taken by an optimized CORDIC-processor. We determine the number of the necessary FPGAs and do a processing speed comparison between FPGA and DSP referring to an application in speech recognition.