Showing papers by "Uwe Meyer-Baese published in 2007"

IPP@HDL: Efficient Intellectual Property Protection Scheme for IP Cores

Abstract: In this paper, a procedure for intellectual property protection (IPP) of digital circuits called IPP@HDL is presented. Its aim is to protect the author rights in the development and distribution of reusable modules by means of an electronic signature. The technique relies on hosting the bits of the digital signature within memory structures or combinational logic that are part of the system, at the high level description of the design. Thus, the area of the system is not increased and the signature is difficult to change or to remove without damaging the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system and without interfering its normal operation. The benefits of the presented procedure are illustrated with programmable logic and cell-based application-specific integrated circuit examples with several signature lengths. These design examples show no performance degradation and a negligible area increase, while probabilistic analyses show that the proposed IPP scheme offers high resistance against attacks.

Intellectual property protection of IP cores through high-level watermarking

Abstract: In this paper a watermarking technique for Intellectual Property Protection (IPP) of FPGA-based systems is proposed. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The proposed watermarking technique relies on a procedure that spreads the digital signature in cells of memory structures at Hardware Description Language (HDL) design level, not increasing the area of the system. This signature is preserved through synthesis, placement and routing processes. The technique includes a procedure for signature extraction requiring minimal modifications to the system. Thus, it is possible to detect the ownership rights without interfering the normal operation of the system and providing high invulnerability. To illustrate the properties of the proposed watermarking technique, both protected and unprotected design examples are compared in terms of area and performance. The analysis of the results shows that the area increase is very low while throughput penalization is almost negligible.

An FPGA based rapid prototyping platform for wavelet coprocessors

Abstract: MatLab/Simulink-based design ”ows are being used by DSP designers to improve time-to-market of FPGA im-plementations. 1 Commonly, digital signal processing cores are integrated in an embedded system as coprocessors.Existing CAD tools do not fully address the integratio n of a DSP coprocessor into an embedded system design.This integration might prove to be time consuming and error prone. It also requires that the DSP designer has anexcellent knowledge of embedded systems and computer ar chitecture details. We present a prototyping platformand design ”ow that allows rapid integration of embedde d systems with a wavelet co processor. The platformcomprises of software and hardware modules that allow a DSP designer a painless integration of a coprocessorwith a PowerPC-based embedded system. The platform has a wide range of applications, from industrial toeducational environments.Keywords: Wavelets, coprocessor, FPGAs 1. INTRODUCTION One of the advantages of FPGA-based embedded systems is their ability to integrate customized user coreswith a soft or hard embedded processor in system-on-a-chip (SoC) solutions. Improvements in an algorithmsexecution time are expected when such customized user cores are used as ha rdware accelerators to calculatecomputationally intensive operations. Wavelets, FFT s, DCT and other transforms are an excellent example ofoperations whose performance can be imp roved by using hardware accelerators.The integration of customized user cores and embedde d processors is done by connecting them together viaa bus. Several options are available to the designer,

Smart altera firmware for DSP with FPGAs

Abstract: Design of current DSP applications using state-of-the art multi-million gates devices requires a broad foundation of engineering skills ranging from knowledge of hardware-efficient DSP algorithms to CAD design tools. The requirement of short time-to-market, however, requires to replace the traditional HDL based designs by a MatLab/Simulink-based design flow. This not only allows the over 1 million MatLab users to design with FPGAs but also to by-pass the hardware design engineer and leads therefore to shorter development time. We have evaluated the Altera/Simulink tool flow used for a University design environment and present design experience of a semester course at FAMU-FSU College of Engineering. We discuss the required background knowledge, key target smart firmware for FPGAs and possible advanced designs, e.g. FFT and multirate filter banks and wavelets designed by students with only basic logic experience.

Digital Signature Embedding Technique for IP Core Protection

Abstract: The intellectual property protection of reusable design modules are becoming a problem with the expansion of this design strategy. This paper propose a new protection method for IP cores to be implemented over FPGAs. The aim is to protect the author rights of reusable IP cores by means of a digital signature that uniquely identifies both the original design and the design recipient. The technique relies on a procedure that spreads a digital signature in cells of look-up tables of designs at HDL design level, not increasing the area of the system. The technique includes a procedure for signature extraction that allows to detect the ownership right without interfering the normal operation of the system and requiring minimal modifications to the system. The IPP technique has been implemented on programmable devices, with negligible performance penalties.

Intellectual Property Protection of HDL IP Cores Through Automated Signature Hosting

Abstract: This paper presents significant improvements to our previous watermarking technique for Intellectual Property Protection (IPP) that enables the protection of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using combinational logic included within the original system. Thus, any attack trying to change or remove the digital signature will damage the design. The technique also includes a procedure for secure signature extraction. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting purposes. The design examples on FPL devices show the effectiveness of this watermarking technique. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.