Showing papers by "Uwe Meyer-Baese published in 2008"

Automated Signature Insertion in Combinational Logic Patterns for HDL IP Core Protection

Abstract: This paper presents significant improvements to previous watermarking technique for intellectual property protection (IPP) of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using resources included within the original system. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system. The new advances refer to increasing the applicability of this watermarking technique to any design and the provision of an automatic tool for signature hosting that, in addition to easy the signature hosting, leads to reduced area penalties. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties.

Space-Efficient Simulation of Quantum Computers

Abstract: Traditional algorithms for simulating quantum computers on classical ones require an exponentially large amount of memory, and so typically cannot simulate general quantum circuits with more than about 30 or so qubits on a typical PC-scale platform with only a few gigabytes of main memory. However, more memory-efficient simulations are possible, requiring only polynomial or even linear space in the size of the quantum circuit being simulated. In this paper, we describe one such technique, which was recently implemented at FSU in the form of a C++ program called SEQCSim, which we releasing publicly. We also discuss the potential benefits of this simulation in quantum computing research and education, and outline some possible directions for further progress.

Intellectual Property Protection of IP Cores at HDL Design Level with Automatic Signature Spreading

Abstract: Watermarking techniques for Intellectual Property Protection (IPP) of IP cores at the HDL design level are proposed in this paper. The basic idea relies on spreading the bits of a digital signature at the HDL design level using combinational logic or look-up structures included within the original system. The techniques also include a secure and non-destructive signature extraction process. Furthermore, in this work the applicability has been extended due to the development of an automated tool for signature spreading purposes. Advances in the automated tool have been achieved by including new search algorithms, as the Simulated Annealing algorithm that achieves additional resources optimization while maintains reduced computation times. A detailed study of the research algorithms is carried out in order to show the advantages in terms of design effort, additional resources and execution times.

HDL-level automated watermarking of IP cores

Abstract: This paper presents significant improvements to our previous watermarking technique for Intellectual Property Protection (IPP) of IP cores. The technique relies on hosting the bits of a digital signature at the HDL design level using resources included within the original system. Thus, any attack trying to change or remove the digital signature will damage the design. The technique also includes a procedure for secure signature extraction requiring minimal modifications to the system. The new advances refer to increasing the applicability of this watermarking technique to any design, not only to those including look-ups, and the provision of an automatic tool for signature hosting purposes. Synthesis results show that the application of the proposed watermarking strategy results in negligible degradation of system performance and very low area penalties and that the use of the automated tool, in addition to easy the signature hosting, leads to reduced area penalties.