Multipliers are vital components of any processor or computing machine. More often than not, performance of microcontrollers and Digital signal processors are evaluated on the basis of number of multiplications performed in unit time. Hence better multiplier architectures are bound to increase the efficiency of the system. Vedic multiplier is one such promising solution. Its simple architecture coupled with increased speed forms an unparalleled combination for serving any complex multiplication computations. Tagged with these highlights, implementing this with reversible logic further reduces power dissipation. Power dissipation is another important constraint in an embedded system which cannot be neglected. In this paper we bring out a Vedic multiplier known as “Urdhva Tiryakbhayam” meaning vertical and crosswise, implemented using reversible logic, which is the first of its kind. This multiplier may find applications in Fast Fourier Transforms (FFTs), and other applications of DSP like imaging, software defined radios, wireless communications.

Design of high speed low power multiplier using Reversible logic: A Vedic mathematical approach

This paper describes the design of high speed Vedic multiplier that uses the techniques of Vedic mathematics based on 16 sutras (algorithms) to improve the performance. In this paper the efficiency of Urdhva Tiryagbhyam (vertical and crosswise) Vedic method for multiplication which is different from the process of normal multiplication is presented. Urdhva-Tiryagbhyam is the most efficient algorithm that gives minimum delay for multiplication for all types of numbers irrespective of their size. Vedic multiplier is coded in Verilog HDL and stimulated and synthesized by using XILINX software 12.2 on Spartan 3E kit. Further the design of array multiplier is compared with the proposed multiplier in terms of delay, memory and power consumption.

Area efficient modified vedic multiplier

This paper briefly describes the Urdhva-Tiryagbhyam Sutra of vedic mathematics and we have designed multiplier based on the sutra. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras which are discovered by Sri Bharti Krishna Tirthaji. In this era of digitalization, it is required to increase the speed of the digital circuits while reducing the on chip area and memory consumption. In various applications of digital signal processing, multiplication is one of the key component. Vedic technique eliminates the unwanted multiplication steps thus reducing the propagation delay in processor and hence reducing the hardware complexity in terms of area and memory requirement. We implement the basic building block: 16 × 16 Vedic multiplier based on Urdhva-Tiryagbhyam Sutra. This Vedic multiplier is coded in VHDL and synthesized and simulated by using Xilinx ISE 10.1. Further the design of array multiplier in VHDL is compared with proposed multiplier in terms of speed and memory.

Design and implementation of 16 × 16 multiplier using Vedic mathematics

*Corresponding author: Email: meetgaur@gmail.com; Tel: +91 9990290384

https://iioab.org/vol5(2)2014/5(2)6-11.pdf

Amino acid frequency distribution among eukaryotic proteins

Multiplier design is always a challenging task; how many ever novel designs are proposed, the user needs demands much more optimized ones. Vedic mathematics is world renowned for its algorithms that yield quicker results, be it for mental calculations or hardware design. Power dissipation is drastically reduced by the use of Reversible logic. The reversible Urdhva Tiryakbhayam Vedic multiplier is one such multiplier which is effective both in terms of speed and power. In this paper we aim to enhance the performance of the previous design. The Total Reversible Logic Implementation Cost (TRLIC) is used as an aid to evaluate the proposed design. This multiplier can be efficiently adopted in designing Fast Fourier Transforms (FFTs) Filters and other applications of DSP like imaging, software defined radios, wireless communications.

Optimized reversible vedic multipliers for high speed low power operations

This paper proposed the design of high speed Vedic Multiplier using the techniques of Ancient Indian Vedic Mathematics that have been modified to improve performance. Vedic Mathematics is the ancient system of mathematics which has a unique technique of calculations based on 16 Sutras. The work has proved the efficiency of Urdhva Triyagbhyam- Vedic method for multiplication which strikes a difference in the actual process of multiplication itself. It enables parallel generation of intermediate products, eliminates unwanted multiplication steps with zeros and scaled to higher bit levels using Karatsuba algorithm with the compatibility to different data types. Urdhva tiryakbhyam Sutra is most efficient Sutra (Algorithm), giving minimum delay for multiplication of all types of numbers, either small or large. Further, the Verilog HDL coding of Urdhva tiryakbhyam Sutra for 32x32 bits multiplication and their FPGA implementation by Xilinx Synthesis Tool on Spartan 3E kit have been done and output has been displayed on LCD of Spartan 3E kit. The synthesis results show that the computation time for calculating the product of 32x32 bits is 31.526 ns.

http://www.ijsrp.org/research_paper_mar2012/ijsrp-Mar-2012-71.pdf

Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques

The number of internet-connected systems has increased by a huge amount in recent years. These systems are highly vulnerable and increasingly at risk from cyber- attacks. These cyber-attacks need more advanced and intelligent cyber defense systems that include agents that can learn to make judgements on their own without consulting human specialists. Deep learning-based reinforcement learning (DRL) is very good at handling complicated, dynamic, and especially high-dimensional cyber protection problems. This article provides a modern network intrusion detection technology, which employs a deep feed-forward neural network method and reinforcement learning, which is based on Q- learning. In order to detect various sorts of intrusions in the network using an automated trial- and-error method and continually improve its detection skills, the Deep Q-Learning (DQL) model is proposed. The accuracy of the model proposed is 91.4%, while the accuracy of other self-taught learning models is 88.4% and it is a similar case for recall rate and precision as well which are 90.2% and 92.8%. Our experimental findings further demonstrate that our suggested DQL beats other comparable machine learning methods and is very good at identifying various intrusion classifications.

V. Charishma

Papers

Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques

Network Intrusion Detection using Deep Reinforcement Learning