When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.

Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators

In this paper, we describe a blind calibration method for timing mismatches in a four-channel time-interleaved analog-to-digital converter (ADC). The proposed method requires that the input signal should be slightly oversampled. This ensures that there exists a frequency band around the zero frequency where the Fourier transforms of the four ADC subchannels contain only three alias components, instead of four. Then the matrix power spectral density (PSD) of the ADC subchannels is rank deficient over this frequency band. Accordingly, when the timing offsets are known, we can construct a filter bank that nulls the vector signal at the ADC outputs. We employ a parametrization of this filter bank to develop an adaptive null steering algorithm for estimating the ADC timing offsets. The null steering filter bank employs seven fixed finite-impulse response filters and three unknown timing offset parameters which are estimated by using an adaptive stochastic gradient technique. A convergence analysis is presented for the blind calibration method. Numerical simulations for a bandlimited white noise input and for inputs containing several sinusoidal components demonstrate the effectiveness of the proposed technique

Blind Calibration of Timing Offsets for Four-Channel Time-Interleaved ADCs

1. Introduction. 2. Low Voltage Issues. 3. Sample-and-Hold Operation. 4. A/D Converters. 5. S/H Circuit Architectures. 6. Sampling with a MOS Transistor Switch. 7. Operational Amplifiers. 8. Clock Generation. 9. Double-Sampling. 10. Switched OpAmp Technique. 11. Other Low-Voltage Techniques. 12. Prototypes and Experimental Results. 13. Conclusions. Appendices: Derivation of OTA GBW Requirement. Optimum Input Capacitance. Saturation Voltage.

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Published methods that employ a filter bank for compensating the timing and bandwidth mismatches of an M-channel time-interleaved analog-to-digital converter (TIADC) were developed based on the fact that each sub-ADC channel is a downsampled version of the analog input. The output of each sub-ADC is filtered in such a way that, when all the filter outputs are summed, the aliasing components are minimized. If each channel of the filter bank has N coefficients, the optimization of the coefficients requires computing the inverse of an MN times MN matrix if the weighted least squares (WLS) technique is used as the optimization tool. In this paper, we present a multichannel filtering approach for TIADC mismatch compensation. We apply the generalized sampling theorem to directly estimate the ideal output of each sub-ADC using the outputs of all the sub-ADCs. If the WLS technique is used as the optimization tool, the dimension of the matrix to be inversed is N times N. For the same number of coefficients (and also the same spurious component performance given sufficient arithmetic precision), our technique is computationally less complex and more robust than the filter-bank approach. If mixed integer linear programming is used as the optimization tool to produce filters with coefficient values that are integer powers of two, our technique produces a saving in computing resources by a factor of approximately (100.2N(M- 1)/(M-1) in the TIADC filter design.

/pdf/time-interleaved-analog-to-digital-converter-compensation-1pujpo1j1e.pdf

Time-Interleaved Analog-to-Digital-Converter Compensation Using Multichannel Filters

With the rapid progress in CMOS compatible microfabrication of biosensors, there is an emerging need to miniaturize biosensor arrays onto the surface of silicon chips that acquire and process sensor data, permitting improved sensitivity, cost and throughput. In this paper, a low power circuit that extracts and digitizes sensor impedance information is presented. Composed of a novel multiplying integrator and a unique bidirectional counter/shifter, the circuit shares resources for impedance extraction and digitization to maximize hardware efficiency. The extremely compact size of the circuit enables the implementation of sensor array microsystems with simultaneous multi-channel readout. Fabricated in 0.5 mum CMOS, the circuit consumes 6 muW at 3 V and occupies only 0.06 mm2, permitting over 100 readout channels within a 3 times 3 mm die. Circuit performance has been verified with a biosensor for gramicidin ion channel embedded in a tethered bilayer lipid membrane.

Compact Low-Power Impedance-to-Digital Converter for Sensor Array Microsystems

Three different CMOS dynamic comparator topologies for pipeline A/D converters, resistive divider, differential pair, and charge distribution comparators, are analyzed. The topologies considered are fully differential, i.e. both sensing and reference voltage inputs are balanced, consist only of a single stage, and feature zero DC power dissipation with a built-in threshold adjusting input stage. Test structures of the comparators, fabricated in 0.35-/spl mu/m CMOS process, are measured to determine the offset properties of the compared topologies.

CMOS dynamic comparators for pipeline A/D converters

In this paper, an effective digital self-calibration method for time-interleaved parallel pipeline ADCs is presented. The method corrects errors of MDACs within the channel ADCs and compensates gain and offset mismatches between parallel channels. According to simulations, 14-bit accuracy can be achieved with 10-bit device matching.

A self-calibration technique for time-interleaved pipeline ADCs

A time-interleaved four-channel pipeline analog-to-digital converter is presented. The A/D converter utilizes a double-sampling, low power, high speed operational amplifier. The maximum sample rate of the converter is 400 MS/s. With a 3.3 V supply voltage, a power consumption of 170 mW is achieved. The circuit is designed with a 0.35 /spl mu/m BiCMOS process and for a full-scale 147.7 MHz input the spurious-free-dynamic-range is 47.8 dB.

A 10-bit 400-MS/s 170 mW 4-times interleaved A/D converter in 0.35-/spl mu/m BiCMOS

This paper presents a 14-bit, 100-MS/s time-interleaved pipeline ADC, which samples input signal from 210-MHz IF-band. Digital self-calibration is employed to compensate gain mismatch and offset between time-interleaved channels as well as mismatches arised from a single ADC channel. A timing skew-insensitive parallel S/H circuit is utilized in order to avoid timing skew between parallel ADC channels. The ADC, fabricated in a 0.35- pm BiCMOS (SiGe) takes an area of 10.2 mm2 reaches an ENOB of 11.4 bits with a 79.9-dB SFDR at 192.5- MHz input and draws 1.4 W from a 3.0-V supply.

A 14b 200MHz IF-sampling A/D converter with 79.9dB SFDR

An IF-sampling parallel S/H circuit is presented. The S/H employs timing skew-insensitive structure using a common sampling switch between two parallel channels. To achieve high sampling linearity the circuit utilizes bootstrapped input switches with a floating bulk and a bottom-plate sampling. A two-stage BiCMOS opamp provides a high DC gain and a wide bandwidth. Simulations give the SFDR of 76 dB with 207.2 MHz, 4 V/sub pp/ differential input signal. The S/H is designed in 0.35-/spl mu/m BiCMOS (SiGe) and consumes 320 mW from a 3.0 V supply. The S/H circuits have been implemented as a front-end of the parallel pipeline ADC.

V. Hakkarainen

Papers

CMOS dynamic comparators for pipeline A/D converters

A self-calibration technique for time-interleaved pipeline ADCs

A 10-bit 400-MS/s 170 mW 4-times interleaved A/D converter in 0.35-/spl mu/m BiCMOS

A 14b 200MHz IF-sampling A/D converter with 79.9dB SFDR

An IF-sampling timing skew-insensitive parallel S/H circuit