A description is given of a delta-sigma ( Delta - Sigma ) modulation and fractional-N frequency division technique for performing indirect digital frequency synthesis using a phase-locked loop (PLL). The use of Delta - Sigma modulation concepts results in beneficial shaping of the phase noise (jitter) introduced by fractional-N division. The technique has the potential to provide low phase noise, fast settling time, and reduced impact of spurious frequencies when compared with existing fractional-N PLL techniques. >

Delta-sigma modulation in fractional-N frequency synthesis

A low cost GMSK (Gaussian minimum shift keying) modulation technique is presented. GMSK is chosen as an example although the technique is suitable for any continuous phase constant envelope modulation with discriminator, differential or coherent detection in the targeted receiver. In this technique, a fractional-N synthesizer is used to control the instantaneous frequency and phase of the phase locked synthesizer output. As a result of this approach, no in-phase and quadrature mixer or D/A converters are required. Furthermore, the desired signal can be generated directly at RF with no IF conversion stages. The look-up table to generate the modulation is only one bit wide. /spl Delta/-/spl Sigma/ techniques are used to obtain high accuracy through the long term average of a sequence of the single bits. The narrow band filtering of the transmit data is accomplished in two parts, a precise digital linear phase band-reject part using the one bit stored ROM look-up table and a less precise low pass analog part inherent to the PLL of the synthesizer. >

A simplified continuous phase modulator technique

A direct digital frequency synthesizer includes a multi-modulus divider, a numerically controlled oscillator and a programmable delay generator. The divider receives an input clock having an input pulse frequency and outputs some integer fraction of those pulses at an instantaneous frequency that is some integer fraction (1/P) of the input frequency. The divider selects between at least two ratios of P (1/P or 1/P+1) in response to a signal from the oscillator. The oscillator receives a value which is the accumulator increment (i.e. the number of divided pulse edges) required before an overflow occurs that causes the divider to change divider ratios in response to receiving an overflow signal. The oscillator also outputs both the overflow signal and a delay signal to the delay generator. The delay signal contains phase-dithering noise that is induced by input into the accumulator of an increment generated from a pseudo-random noise generator.

Direct digital synthesizer for reference frequency generation

A digital compensation method is described that allows fractional-N frequency synthesizers to be directly modulated at high data rates while simultaneously achieving good noise performance. The technique allows digital phase/frequency modulation to be achieved at high data rates (> 1 Mbit/s) without mixers or D/A converters in the modulation path. The resulting transmitter design is primarily digital in nature and reduced to its fundamental components — a frequency synthesizer that accurately sets the output frequency, and a digital transmit filter that provides good spectral efficiency. The synthesizer is implemented as a phase locked loop (PLL). To achieve good noise performance with a simple design, the PLL bandwidth is set to a low value relative to the data bandwidth. A digital compensation filter is then used to undo the attenuation of the PLL transfer function seen by the data. This filter adds little complexity to the transmitter architecture since it can be combined with the digital transmit filter; the overall filter is efficiently implemented by using a ROM to perform the required convolution with input data. Measured results from a prototype indicate that good performance, low power operation, and high levels of integration are achieved with the approach. Specifically, a 1.8 GHz transmitter was built that supports data rates in excess of 2.5 Mbit/s using Gaussian Frequency Shift Keying (GFSK), the same modulation method used in the digital enhanced cordless telecommunications (DECT) standard. The phase noise of the unmodulated synthesizer was measured at -132 dBc/Hz at 5 MHz offset from the carrier frequency. (Simulations show that the modulated synthesizer achieves -132 dBc/Hz at 5 MHz offset at 1.25 Mbit/s data rate.) The key circuits in the prototype were implemented on a custom, 0.6 um CMOS IC that consumes 27 mW. Included on the IC are an on-chip filter that requires no tuning or external components, a digital MASH Sigma-Delta converter that achieves low power operation through pipelining, and an asynchronous, 64 modulus divider (prescaler) that supports any divide value between 32 and 63.5 in half cycle increments of its input. An external divide-by-2 prescaler allows the divider to operate at half

Techniques for high data rate modulation and low power operation of fractional-N frequency synthesizers

Spur reduction techniques used in direct digital synthesizers (DDSs) or numerically controlled oscillators (NCOs) are reviewed. First, the classification and operation of conventional DDSs are reviewed. The pulse output DDS, the sine output DDS, the fractional divider, and the phase interpolation DDS are considered. It is shown that DDSs produce spurs as well as the desired output frequency due to the aliasing of harmonic imperfections in the generated waveform. Next, spur reduction techniques which reduce spurs by destroying the coherence of the aliasing process are discussed. Architectures described are the spurless fractional divider, the Wheatley jitter injection DDS, the randomized DAC (digital-to-analog) DDS, and the nonuniform clock DDS. The spur reduction and phase jitter properties of each architecture are also discussed. >

V. Reinhardt

Papers

A Short Survey of Frequency Synthesizer Techniques

A SEORT SURVEY OF PBeQuElvCy SYllTBESIZEB TECHNIQUES