Indirect branch prediction is likely to become increasingly important in the future because indirect branches occur more frequently in object-oriented programs. With misprediction rates of around 25% on current processors, indirect branches can incur a significant fraction of branch misprediction overhead even though they remain less frequent than the more predictable conditional branches. We investigate a wide range of two-level predictors dedicated exclusively to indirect branches. Starting with predictors that use full-precision addresses and unlimited tables, we progressively introduce hardware constraints and minimize the loss of predictor performance at each step. For programs from the SPECint95 suite as well as a suite of large C++ applications, a two-level predictor achieves a misprediction rate of 9.8% with a 1K-entry table and 7.3% with an 8K-entry table, representing more than a threefold improvement over an ideal BTB. A hybrid predictor further reduces the misprediction rates to 8.98% (1K) and 5.95% (8K).

Accurate indirect branch prediction

Two-level predictors improve branch prediction accuracy by allowing predictor tables to hold multiple predictions per branch. Unfortunately, the accuracy of such predictors is impaired by two detrimental effects. Capacity misses increase since each branch may occupy many entries, depending on the number of different path histories leading up to the branch. The working set of a given program therefore increases with history length. Similarly, cold start misses increase with history length since the predictor must first store a prediction separately for each history pattern before it can predict branches with that history. We describe a new hybrid predictor architecture, cascaded branch prediction, which can alleviate both of these effects while retaining the superior accuracy of two level predictors. Cascaded predictors dynamically classify and predict easily predicted branches using an inexpensive predictor, preventing insertion of these branches into a more powerful second stage predictor. We show that for path-based indirect branch predictors, cascaded prediction obtains prediction rates equivalent to that of two-level predictors at approximately one fourth the cost. For example, a cascaded predictor with 64+1024 entries achieves the same prediction accuracy as a 4096-entry two-level predictor. Although we have evaluated cascaded prediction only on indirect branches, we believe that it could also improve conditional branch prediction and value prediction.

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The cascaded predictor: economical and adaptive branch target prediction

Virtual machines (VMs) are commonly used to distribute programs in an architecture-neutral format, which can easily be interpreted or compiled. A long-running question in the design of VMs is whether stack architecture or register architecture can be implemented more efficiently with an interpreter. We extend existing work on comparing virtual stack and virtual register architectures in two ways. Firstly, our translation from stack to register code is much more sophisticated. The result is that we eliminate an average of more than 47% of executed VM instructions, with the register machine bytecode size only 25% larger than that of the corresponding stack bytecode. Secondly we present an implementation of a register machine in a fully standard-compliant implementation of the Java VM. We find that, on the Pentium 4, the register architecture requires an average of 32.3% less time to execute standard benchmarks if dispatch is performed using a C switch statement. Even if more efficient threaded dispatch is available (which requires labels as first class values), the reduction in running time is still approximately 26.5% for the register architecture.

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Virtual machine showdown: stack versus registers

A method for forwarding operands directly between instructions operates in a computer central processing unit. Values for registers, condition codes, stack locations and memory storage locations are routed directly from the program instructions or microcode that alter them to the instructions that use those operands. Instructions that have received all needed operands are started and their resulting output operands are forwarded to other instructions. With direct forwarding of operands, normal locations for operands may often be skipped so that simpler designs can be employed in constructing the operand storage for register files and stacks. Operands receiving newer values never appear in program-visible locations if the prior values were forwarded to all instructions that might need them and those receiving instructions are completed. In executing program loops, loop-dependent variables are identified. A method is shown whereby multiple loop-dependent operands are computed substantially simultaneously. In favorable circumstances multiple iterations of one or more loops are executed in parallel. The number of iterations is computed and then governs the number of loop iterations executed. Storage of results in architected, generally available areas is avoided where operands are no longer needed after loop iteration execution.

Method and apparatus for annotating operands in a computer system with source instruction identifiers

Interpreters designed for high general-purpose performance typically perform a large number of indirect branches (3.2%–13% of all executed instructions in our benchmarks). These branches consume more than half of the run-time in a number of configurations we simulated. We evaluate how accurate various existing and proposed branch prediction schemes are on a number of interpreters, how the mispredictions affect the performance of the interpreters and how two different interpreter implementation techniques perform with various branch predictors. We also suggest various ways in which hardware designers, C compiler writers, and interpreter writers can improve the performance of interpreters.

The Structure and Performance of Efficient Interpreters.

Branch effects are the biggest obstacle to gaining significant speedups when running general purpose code on instruction level parallel machines. The article presents a survey which compares current branch effect reduction techniques, offering hope for greater gains. We believe this survey is timely because research is bearing much fruit: speedups of 10 or more are being demonstrated in research simulations and may be realized in hardware within a few years. The hardware required for large scale exploitation is great, but the density of transistors per chip is increasing exponentially, with estimates of 50 to 100 million transistors per chip by the year 2000.

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V. Sindagi

Papers

Branch effect reduction techniques