In this paper we have designed an energy efficient multiplier using Nikhilam Navatashcaramam Dashatah Vedic technique. Vedic mathematics consists of 16 sutras and these sutras were used by our ancient scholars for doing there calculation faster, when there were no computers and calculators. Nikhilam Navatasaman is a Sanskrit word which menas “all from 9 and the last from 10”. In today’s work the demand is high speed, efficiency and should take lesser time. Appling these Vedic techniques reduces the system complexity, execution time, area, power and is stable and hence is efficient method. In this paper we have designed an energy efficient multiplier that consists of three inputs and one output. The temperature has been kept constant that is 25 degree Celsius. Airflow has been kept 250 LFM and medium Heat sink. IO Standards has been varied in order to achieve an energy efficient device. In this paper we have taken HSTL (High Speed Transceiver Logic) IOSTANDARD. In order to achieve speed and high performance in addition to energy efficiency, HSTL IO standard is used. HSTL family consists of HSTL _I, HSTL_II, HSTL_I_18 and HSTL_II_18, HSTL_I_12 and the analysis has been done on these IO standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA.

HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

To provide context-based personalized services utilizing smart appliances in a smart home environment, we propose a framework for PersonAlized Service disCovery Using FuZZY-based CBR and Context Ontology (PASCUZZY). Basically, the PASCUZZY framework is implemented on case-based context ontology. To generate and manage the case instances on the case-based context ontology, we adopt the fuzzy set theory to transpose numerical-type context data sensed from the surrounding environment. The context is transposed to linguistic-type context instances on the context ontology. In addition, to formalize and manage the context and services as multi-attributed data, the context ontology was developed reflecting the structure of cases borrowed from case-based reasoning. Furthermore, we propose adaptation methods to adjust the generic fuzzy membership functions depending on the inhabitants' context. It is performed by modifying the values of the membership number and/or modifying the numbers of the linguistic terms that are based on the inhabitants' context to affect the membership numbers. The adapted membership functions return the personalized degree of memberships depending on the specialized context of a specific fuzzy variable. Inevitably, the number of cases on the case-based context ontology will be increased from time to time. We apply Ward's method not only to reduce the search effort via a hierarchical clustering on the case-based context ontology but also to find the most similar service as a solution to the new context. To verify the superiority of the PASCUZZY framework, we perform two kinds of evaluations. First, we evaluate the effectiveness of the adaptation of the fuzzy membership functions. Second, we verify the effectiveness of the application of a clustering method to the case instances of the case-based context ontology to identify the most similar service. Results of the experiment verified the effectiveness and superiority of the PASCUZZY framework.

Case-based context ontology construction using fuzzy set theory for personalized service in a smart home environment

Rapidly growing technology has raised demands for fast and efficient real time digital signal processing applications. Multiplication is one of the primary arithmetic operations every application demands. A large number of multiplier designs have been developed to enhance their speed. Active research over decades has lead to the emergence of Vedic Multipliers as one of the fastest and low power multiplier over traditional array and booth multipliers. Vedic Multiplier deals with a total of sixteen sutras or algorithms for predominantly logical operations. A large number of them have been proposed using Urdhava Tiryakbhyam sutra rendering them most efficient in terms of speed. The objective of this paper is to encapsulate an array of applications of Vedic Multiplier in the vast domain of Image processing and Digital signal processing, particularly the different modifications of existing Vedic Multiplier architectures enhancing their speed and performance parameters.

Applications of vedic multiplier designs - A review

The problem of faults is growing exponentially due to embedded memory area on-chip is increasing and memory density is growing. There are two types of memory single port and multiported comparing these two memories multiported memory have ability to support more efficient execution of operation and high speed performance. Built-in self test is used to detect and repair the faults in multiported memory. The microcode based Asynchronous p-MBIST is implemented using FPGA and compared with similar feature Synchronous P-MBIST.

Implementation of BIST technology for fault detection and repair of the multiported memory using FPGA

Testing embedded memories in a chip can be very challenging due to their high-density nature and manufactured using very deep submicron (VDSM) technologies. In this review paper, functional fault models which may exist in the memory are described, in terms of their definition and detection requirement. Several memory testing algorithms that are used in memory built-in self-test (BIST) are discussed, in terms of test operation sequences, fault detection ability, and also test complexity. From the studies, it shows that tests with 22 N of complexity such as March SS and March AB are needed to detect all static unlinked or simple faults within the memory cells. The N in the algorithm complexity refers to Nx*Ny*Nz whereby Nx represents the number of rows, Ny represents the number of columns and Nz represents the number of banks. This paper also looks into optimization and further improvement that can be achieved on existing March test algorithms to increase the fault coverage or to reduce the test complexity.

A review paper on memory fault models and test algorithms

In this era of rapidly growing technology, Digital Signal Processing (DSP) is one of the core technologies having applications in various fields. This paper discusses about the design of an 8 bit fixed point, asynchronous Vedic DSP processor core. This novel architecture exploits the principles of asynchronous design using micro-pipelining methodology and also Vedic mathematics. Asynchronous design style eliminates clocking issues and reduces about 40% of the total power consumption [12]. An efficient Vedic multiplier proposed in this paper utilizes the following sutras: Urdhva — tiryagbhyam, Nikhilam Navatashcaramam Dastaha, Ekadhikena Purvena, Ekanyunena Purvena, Anurupyena, Antyayor Dasakepi. A novel Vedic divider is also presented using the following sutras: Nikhilam, Paravartya Yojayet, Urdhva Tiryakbhyam and Dhvijanka. This paper deals the novel architecture and design of low power Vedic DSP core using asynchronous logic style.

Design of novel Vedic asynchronous digital signal processor core

In today's VLSI world, the designers concentrate on low power design, neglecting the test methodology Defining low power test methodology is the need of the day In this paper, Microcode based Asynchronous P-MBIST is implemented, measured and compared with similar feature Synchronous PMBIST The implemented core has given Power, Area advantage of 9544%, 2395% respectively but with increased Timing of 1004% over Synchronous P-MBIST The design is a synthesizable core which can be extended to multiple memory fault testing The implemented design is synthesized over two different technology 180nm & 45nm Even, the methodology adopted has given power advantage in scaled down technology

Performance analysis of low power microcode based asynchronous P-MBIST

Processing of the multiple data streams demand highperformance multiple transfers overburden the Processor System on Chips (SoC) in real time multimedia processing applications. High performance direct memory access (DMA) controller eases the processor as it performs bulk data transfer without the intervention of processor. This is true even in most artificial intelligence (AI) based systems and interleaving functions in communication systems where high-speed bulk data transfers are required. This is achieved by the design of Enhanced Direct Memory Access (EDMA) Controller, for high speed bulk data transfers. Paper presents the design of enhanced DMA core which is synthesizable ready to integrate for high performance AI based Digital Signal Processing SoC. The EDMA core is used for flexible Memory Access and bulk data transfers. EDMA core support several methods for data transfer between an input or output (I/O) device and the core processing unit. The processor in the SoC is used to program the Direct Memory Access (DMA) transfer instructions and actual transfers are performed by the EDMA core without the interference of processor. The EDMA design supports flexible addressing modes like linear, circular, step for bulk data transfers. The EDMA core is planned to be verified with test cases as in realistic application scenarios of interleaving, real time video processing.

Design and Implementation of EDMA Controller for AI based DSP SoCs for Real- Time Multimedia Processing

Introduction -- SoC design methodology -- System on Chip Components -- DFT and Synthesis -- Static timing Analysis (STA) -- VLSI System Verification -- Physical Design -- Advanced Techniques: Low power UPF flow -- Reference Design: Specification to Layout.

Veena S. Chakravarthi

Papers

Design of novel Vedic asynchronous digital signal processor core

Performance analysis of low power microcode based asynchronous P-MBIST

Design and Implementation of EDMA Controller for AI based DSP SoCs for Real- Time Multimedia Processing

A Practical Approach to VLSI System on Chip (Soc) Design: A Comprehensive Guide

Proceedings of International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking (VCASAN-2013)