An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A light emitting die package includes a substrate, a reflector plate, and a lens. The substrate has traces for connecting an external electrical power source to a light emitting diode (LED) at a mounting pad. The reflector plate is coupled to the substrate and substantially surrounds the mounting pad, and includes a reflective surface to direct light from the LED in a desired direction. The lens is free to move relative to the reflector plate and is capable of being raised or lowered by the encapsulant that wets and adheres to it and is placed at an optimal distance from the LED chip(s). Heat generated by the LED during operation is drawn away from the LED by both the substrate (acting as a bottom heat sink) and the reflector plate (acting as a top heat sink).

Power surface mount light emitting die package

A semiconductor device including a substrate, solder bumps provided on a lower major surface of the substrate, a semiconductor chip provided on an upper major surface of the substrate, a resin package body provided on the upper major surface of the substrate so as to bury the semiconductor chip therein, a thermally conductive frame member having a flange part supporting the substrate at a rim part of the substrate, wherein the thermal conductive frame member has a thermal conductivity substantially larger than that of the resin package body and extending along to and in an intimate contact with side walls of the resin package body.

Semiconductor device in a resin package housed in a frame having high thermal conductivity

A semiconductor package substrate is provided, which can meet the move toward high integration of semiconductors. A nickel layer is plated on an electroplated copper foil to form a wiring pattern. An LSI chip is mounted on the copper foil, and terminals of the LSI chip and the wiring pattern are connected by wire bonding, followed by sealing with a semiconductor-sealing epoxy resin. Only the copper foil is dissolved away with an alkali etchant to expose nickel. With a nickel stripper having low copper-dissolving power, the nickel layer is removed to expose the wiring pattern. A solder resist is coated, and a pattern is formed in such a way that connecting terminal portions are exposed. Solder balls are placed at the exposed portions of the wiring pattern and are then fused. The wiring pattern is connected to an external printed board via the solder balls.

Fabrication process of semiconductor package and semiconductor package

A microelectronic package includes a microelectronic element having faces and contacts, the microelectronic element having an outer perimeter, and a substrate overlying and spaced from a first face of the microelectronic element, whereby an outer region of the substrate extends beyond the outer perimeter of the microelectronic element. The microelectronic package includes a plurality of etched conductive posts exposed at a surface of the substrate and being electrically interconnected with the microelectronic element, whereby at least one of the etched conductive posts is disposed in the outer region of the substrate. The package includes an encapsulating mold material in contact with the microelectronic element and overlying the outer region of the substrate, the encapsulating mold material extending outside of the etched conductive posts for defining an outermost edge of the microelectronic package.

Microelectronic packages and methods therefor

A pad array semiconductor device (35) includes a thermal conductor (28) integrated into a circuitized substrate (14). A semiconductor die (12) is mounted on the substrate overlying the thermal conductor to establish a thermal path away from the die. The thermal conductor may also be covered or surrounded by a metallized area (37, 39), which together may serve as a ground plane in the device. Preferably one or more terminals (26) are attached to the thermal conductor for improved thermal and electrical performance. One method of integrating the thermal conductor in the substrate is to position a metal plug into an opening 30 of the substrate. The plug is then compressed or otherwise plastically deformed to fill the opening and create a substantially planar substrate surface.

Pad array semiconductor device with thermal conductor and process for making the same

A ball grid array semiconductor device (30) includes a plurality of conductive balls (36) and a plurality of conductive castellations (18) around its periphery as redundant electrical connections to a semiconductor die (12). During testing of the device in a test socket (50), the conductive castellations are contacted by test contacts (54). The test contacts do not come in physical contact with the conductive balls. As a result, when testing is performed at elevated temperatures near the melting point of the conductive balls, the conductive balls are not deformed by the test contacts, thereby eliminating cosmetic-defects. Additionally, the absence of physical contact between the conductive balls and the test contacts during testing reduces the likelihood that conductive balls will inadvertently fuse to the test socket or create solder build-up on the test contacts.

Method for testing a ball grid array semiconductor device and a device for such testing

Routing density of a wiring substrate (10) is increased by providing a nested plating bus (18) as a supplement to an external plating bus (16). A first group of conductive traces (14) is connected to the nested plating bus, while another group of traces is connected to the external plating bus. After the conductive elements are plated, the nested plating bus is removed by etching, milling, or stamping techniques. Use of a nested plating bus increases I/O count for a given substrate area and/or reduces the need to have routing on more than one layer of the substrate.

Method for plating using nested plating buses and semiconductor device having the same

PURPOSE: To provide a pad array semiconductor device possessed of a thermal conductor formed in one piece with a circuit board. CONSTITUTION: A semiconductor die 12 is mounted on a thermal conductor on a board, whereby heat released from the die 12 is dissipated. The thermal conductor may be covered or surrounded with metallized regions 37 and 39, wherein the regions 37 and 39 serve as a grounding plane for a device. It is preferable that one or more terminals 26 are fixed to the thermal conductor so as to improve it in thermal and electrical properties. One method to join the thermal conductor to the board is than a metal plug is placed on an opening 30 provided in the board. Thereafter, the plug is compressed or elastically deformed so as to stop up the opening, and the surface of the board is made substantially flat.

Victor K. Nomi

Papers

Pad array semiconductor device with thermal conductor and process for making the same

Method for testing a ball grid array semiconductor device and a device for such testing

Method for plating using nested plating buses and semiconductor device having the same

Pad-array semiconductor provided with heat conductor and its manufacture