Lithography is a field in which advances proceed at a swift pace. This book was written to address several needs, and the revisions for the second edition were made with those original objectives in mind. Many new topics have been included in this text commensurate with the progress that has taken place during the past few years, and several subjects are discussed in more detail. This book is intended to serve as an introduction to the science of microlithography for people who are unfamiliar with the subject. Topics directly related to the tools used to manufacture integrated circuits are addressed in depth, including such topics as overlay, the stages of exposure, tools, and light sources. This text also contains numerous references for students who want to investigate particular topics in more detail, and they provide the experienced lithographer with lists of references by topic as well. It is expected that the reader of this book will have a foundation in basic physics and chemistry. No topics will require knowledge of mathematics beyond elementary calculus.

Principles of Lithography

In all imaging systems, the forward process introduces undesirable effects that cause the output signal to be a distorted version of the input. A typical example is of course the blur introduced by the aperture. When the input to such systems can be controlled, prewarping techniques can be employed which consist of systematically modifying the input such that it (at least approximately) cancels out (or compensates for) the process losses. In this paper, we focus on the optical proximity correction mask design problem for "optical microlithography," a process similar to photographic printing used for transferring binary circuit patterns onto silicon wafers. We consider the idealized case of an incoherent imaging system and solve an inverse problem which is an approximation of the real-world optical lithography problem. Our algorithm is based on pixel-based mask representation and uses a continuous function formulation. We also employ the regularization framework to control the tone and complexity of the synthesized masks. Finally, we discuss the extension of our framework to coherent and (the more practical) partially coherent imaging systems

Mask Design for Optical Microlithography—An Inverse Imaging Problem

Numerical optimization is an important tool in the field of computational physics in general and in nano-optics in specific. It has attracted attention with the increase in complexity of structures...

Benchmarking Five Global Optimization Approaches for Nano-optical Shape Optimization and Parameter Reconstruction

Optical lithography has enabled the printing of progressively smaller circuit patterns over the years. However, as the feature size shrinks, the lithographic process variation becomes more pronounced. Source-mask optimization (SMO) is a current technology allowing a co-design of the source and the mask for higher resolution imaging. In this paper, we develop a pixelated SMO using inverse imaging, and incorporate the statistical variations explicitly in an optimization framework. Simulation results demonstrate its efficacy in process robustness enhancement.

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Pixelated source mask optimization for process robustness in optical lithography

Immersion lithography systems with hyper-numerical aperture (hyper-NA) (NA>1) have become indispensable in nanolithography for technology nodes of 45 nm and beyond. Source and mask optimization (SMO) has emerged as a key technique used to further improve the imaging performance of immersion lithography. Recently, a set of pixelated gradient-based SMO approaches were proposed under the scalar imaging models, which are inaccurate for hyper-NA settings. This paper focuses on developing pixelated gradient-based SMO algorithms based on a vector imaging model that is accurate for current immersion lithography. To achieve this goal, an integrative and analytic vector imaging model is first used to formulate the simultaneous SMO (SISMO) and sequential SMO (SESMO) frameworks. A gradient-based algorithm is then exploited to jointly optimize the source and mask. Subsequently, this paper studies and compares the performance of individual source optimization (SO), individual mask optimization (MO), SISMO, and SESMO. Finally, a hybrid SMO (HSMO) approach is proposed to take full advantage of SO, SISMO, and MO, consequently achieving superior performance.

Pixelated source and mask optimization for immersion lithography.

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM and RET flow required to
continue shrinking designs in the low-k1 lithography regime. The ability to model and minimize MEEF during
lithography optimization and RET application is essential to obtain a usable process window (PW). In Inverse
Lithography Technology (ILT), MEEF can be included in the cost function as a nonlinear factor, so that the inversion
minimizes MEEF, in addition to optimizing PW and edge placement error (EPE). ILT has been shown to optimize
masks for a given source. Using ILT for contemporaneous Source and Mask co-Optimization (SMO) can provide further
benefit by balancing the complexity of mask and source. Results demonstrating the benefits of "MEEF-aware" ILT and
SMO for advanced technology nodes are presented in this paper.

Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)

Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model- based OPC in the search for op timal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm & below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Insp ection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Lu minescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with vary ing degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost. Keywords : Inverse Lithography Technology, 32 nm & below, low-k1, depth of focus, lithographic performance, mask cost, OPC, RET, MEEF, SRAF

Trade-off between inverse lithography mask complexity and lithographic performance

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography
presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years,
source optimization and mask pattern correction have been conducted as two separate RET steps. For source
optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not
considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been
introduced for the lithography development stage. The next important step would be the extension of SMO, and in
particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set
Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or
ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device
results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO
and its extendibility to full chip designs.

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

This paper presents a consistent and modularized approach to modeling projection optics. Vector nature of light
and polarization effect are considered from the very beginning at source, through mask and projection lens down
into film stack. High-NA and immersion effect are also included. Of particular interest is the formulation of
a modularized framework for computing optical images that allows various mask models (a thin-mask model,
an empirical approximate mask model, or a rigorous mask 3D solver) to be used. We demonstrate that under
Kirchoff thin-mask assumption our formulation is the same as Smythe formula. A compact film-stack model is
formulated. The formulation is first presented in Abbe's source integration approach and then reformulated in
Hopkins' TCC approach which allows for a SVD decomposition, which is computationally more efficient for a
fixed optical setting.

Toward a Consistent and Accurate Approach to Modeling Projection Optics

Contribution of mask line edge roughness (LER) to resist LER on wafers was studied both by simulations and experiments. LER transfer function (LTF) introduced by Naulleau and Gallatin was generalized to include the effect of mask error enhancement factor (MEEF). Low spatial frequency part of LTF was enhanced by MEEF while high spatial frequency part was suppressed due to the numerical aperture limit of a stepper. Our model was experimentally verified as follows. First LER of a mask was measured by a scanning electron microscope. Then the mask LER was multiplied by LTF to simulate the aerial image LER on wafers. It was confirmed that the simulated LER agreed well with the LER measured by AIMS TM . Based on our model the contribution of the mask LER to the resist LER on wafers was estimated. According to our estimation the requirement of the mask LER should be as tight as that of the resist LER on wafers.

Vikram Tolani

Papers

Considering MEEF in inverse lithography technology (ILT) and source mask optimization (SMO)

Trade-off between inverse lithography mask complexity and lithographic performance

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

Toward a Consistent and Accurate Approach to Modeling Projection Optics

LER Transfer from a Mask to Wafers