In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563 $\mu $ W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664 $\mu $ W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79- $\mu $ W (53.36- $\mu $ W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.

Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as it lowers power consumption by using XOR (3T) logic circuits. Gate Diffusion Input (GDI) technique of low-power digital combinatorial circuit design is also described. This technique helps in reducing the power consumption and the area of digital circuits while maintaining low complexity of logic design. This paper analyses, evaluates and compares the performance of various adder circuits. Several simulations conducted using different voltage supplies, load capacitors and temperature variation demonstrate the superiority of the XOR (3T) based full adder designs in term of delay, power and power delay product (PDP) compared to the other full adder circuits. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid full adder circuits in terms of power, delay and power delay product (PDP).

https://aircconline.com/vlsics/V3N2/3212vlsics19.pdf

Comparative Performance Analysis of XOR- XNOR Function Based High-Speed CMOS Full Adder Circuits For Low Voltage VLSI Design

Since there is a swift technological progress going on in the recent years, semiconductor industry evolved to such an extend that requirement of optimal performance in electronic circuits have become essential. Therefore, there is high requirement of energy efficient fast circuit designs in modern Integrated Circuits (IC). Comparison of two binary digits is one of the fundamental arithmetic operations in Arithmetic Logic Units (ALU) of ICs and processors. A hybrid design approach for implementing a two-bit Magnitude Comparator (MC) has been proposed in this work. The hybrid design consists of three different logic techniques namely: (a) Pass Transistor Logic (PTL), (b) Transmission Gate Logic (TGL) and (c) Conventional Static CMOS Logic (C-CMOS logic). The effectiveness of the proposed design has been compared with 6 state of art two-bit magnitude comparators using Cadence tools in 90 nm technology node. The proposed design showed best perormacne in case of delay and Power Delay Product (PDP) which proved the effectiveness of the design, Moreover, power consumption of the design is also low which makes it highly usable for portable devices that requires low-power consumption.

Design of a Two-Bit Magnitude Comparator Based on Pass Transistor, Transmission Gate and Conventional Static CMOS Logic

Performance evolution of 4-b bit MAC unit using hybrid GDI and transmission gate based adder and multiplier circuits in 180 and 90 nm technology

Limiting or reducing the power consumption of the digital circuits for calculation is now the main concern in nanoelectronic domain. For this purpose, spintronic devices are proposed to combine or even replace complementary metal-oxide semiconductor (CMOS) technology for the implementation of integrated circuits. One of the most promising solutions is all spin logic (ASL) device, due to a low power consumption, high switching speed and the compatibility with CMOS. In this paper, we propose a one-bit full-adder and a multi-bits adder circuits relying on ASL devices. The performances of the circuits are evaluated with transient simulation using a compact model of ASL devices developed in Cadence. Finally, ASL device parameters are explored for optimization.

Full-adder circuit design based on all-spin logic device

This paper presents a comparative study of highspeed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR (4T) design full adder circuits combined in a single unit. This technique helps in reducing the power consumption and the propagation delay while maintaining low complexity of logic design. Simulation results illustrate the superiority of the designed adder circuits against the conventional CMOS, TG and Hybrid adder circuits in terms of power, delay and power delay product (PDP) at low voltage. Noise analysis shows designed full adder circuit's work at high frequency and high temperature satisfactorily. Simulation results reveal that the designed circuits exhibit lower PDP, more power efficiency and faster when compared to the available full adder circuits at low voltage. The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

Vishant

Papers

Design analysis of XOR (4T) based low voltage CMOS full adder circuit