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Vyas R. Murnal

Researcher at SDM College of Engineering and Technology

Publications -  4
Citations -  11

Vyas R. Murnal is an academic researcher from SDM College of Engineering and Technology. The author has contributed to research in topics: Scattering & Ballistic conduction. The author has an hindex of 1, co-authored 3 publications receiving 5 citations.

Papers
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Journal ArticleDOI

A quasi-ballistic drain current, charge and capacitance model with positional carrier scattering dependency valid for symmetric DG MOSFETs in nanoscale regime.

TL;DR: A physically valid quasi-ballistic drain current model applicable for nanoscale symmetric Double Gate (SDG) MOSFETs and shown to be continuous in terms of terminal charges and capacitances in all regions of operation.
Proceedings ArticleDOI

A Quasi-Ballistic Drain current model with Positional Scattering Dependency applicable for Nanoscale DG MOSFETs

TL;DR: In this article, a simple physics-based quasi-ballistic drain current model is proposed for nanoscale double gate MOSFETs. But the model considers scattering effects that occur in real-scale devices, in terms of transmission and reflection co-efficients related to scattering theory.
Book ChapterDOI

An Analytic Potential Based Velocity Saturated Drain Current, Charge and Capacitance Model for Short Channel Symmetric Double Gate MOSFETs

TL;DR: In this article, the authors presented a velocity saturated and channel length modulated drain current, charge and capacitance model for a symmetric double gate (SDG) short channel MOSFET.
Journal ArticleDOI

An optimized nanoscale Quasi-Ballistic DG MOSFET model with diffusive carrier scattering dependency

TL;DR: In this article , the authors proposed a physically accurate quasi-ballistic drain current model valid for Double Gate (DG) MOSFETs in the nanoscale regime, which considers the carrier scattering physics and includes both ballistic and diffusive transport.