The design and construction of the silicon strip microvertex detector (SMD) of the L3 experiment at LEP are described. We present the sensors, readout electronics, data acquisition system, mechanical assembly and support, displacement monitoring systems and radiation monitoring system of the recently installed double-sided, double-layered SMD. This detector utilizes novel and sophisticated techniques for its readout.

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The L3 silicon microvertex detector

Switched capacitor arrays (SCA) ASICs are becoming more and more popular for the readout of detector signals, since the sampling frequency of typically several gigasamples per second allows excellent pile-up rejection and time measurements. They suffer however from the fact that their sampling bins are not equidistant in time, given by limitations of the chip manufacturing. In the past, this has limited time measurements of optimal signals to standard deviations (σ) of about 4-25 ps in accuracy for the split pulse test, depending on the specific chip. This paper introduces a novel time calibration, which determines the true sampling speed of an SCA. Additionally, for two independently running SCA chips, the achieved time resolution improved to less than 3 ps (σ) independently from the delay for the split pulse test, when simply applying a linear interpolation. When using a more advanced analyzing technique for the split pulse test with a single SCA, this limit is pushed below 1 ps (σ) for delays up to 8 ns. Various test measurements with different boards based on the DRS4 ASIC indicate that the new calibration is stable over time but not over larger temperature variations.

Novel Calibration Method for Switched Capacitor Arrays Enables Time Measurements With Sub-Picosecond Resolution

The development of large area 2-dimensional amorphous silicon image sensor arrays has taken nearly ten years. At the time of writing, these devices are being introduced into the market for digital X-ray imaging applications such as medical radiography and non-destructive testing. This chapter describes the arrays, the range of applications and why the amorphous silicon technology is well matched to the particular needs of X-ray imaging.

Large Area Image Sensor Arrays

Three novel integrated CMOS active pixel sensor circuits for vertex detector applications have been designed with the goal of increased signal-to-noise ratio and speed. First, a large-area native epitaxial silicon photogate sensor was designed to increase the charge collected per hit pixel and to reduce charge diffusion to neighboring pixels. High charge to voltage conversion is maintained by subsequent charge transfer to a low capacitance readout node. Second, a per-pixel correlated double sampling kT/C reset noise reduction circuit was tested. It requires only one read, as compared to two for typical double sampling in active pixel sensors, and no off-pixel storage or subtraction is needed. The technique reduced input-referred temporal noise by a factor of 2.5 to a measured 15.6 e/sup -/, rms. Finally, a column-level active reset technique was designed that suppresses kT/C reset noise. It reduced noise by up to a factor of 7.6, to an estimated 8.3 input-referred electrons, rms. The technique also dramatically reduces fixed pattern (pedestal) noise, by up to a factor of 21. This may reduce pixel-by-pixel pedestal differences enough to permit sparse data scan without per-pixel offset corrections.

https://www.hep.ph.imperial.ac.uk/calice/mapsMeetings/070119ral/active-reset01344332.pdf

Novel integrated CMOS sensor circuits

Silicon detector systems in high energy physics

A full-custom CMOS integrated circuit for silicon strip detector systems has been designed, fabricated, and tested. The circuit contains 128 parallel data-acquisition channels and considerable peripheral circuitry. Each channel consists of a low-noise, low-power, charge-sensitive amplifier, a multistage autobalanced comparator, an analog multiplexer, nearest-neighbor logic, priority-search logic, and a share of a position-encoding read-only memory. The analog system can substract both detector pedestal and leakage current on a channel-by-channel basis. A key feature of this design is the inclusion of on-chip sparse read-out circuitry, which allows efficient management of low-occupancy events. Designed for use at the Collider Detector Facility (CDF) at Fermilab, the circuit is suitable for large-scale silicon detector systems requiring a large, dense array of fast, low-power electronics. >

A flexible 128 channel silicon strip detector instrumentation integrated circuit with sparse data readout

A description is given of a system that has been built and operated for distributing high voltage to 2000 channels of proportional chambers in the gas calorimeters of the CDF detector. The system consists of CAMAC-based controllers and distribution modules in the Rabbit hardware standard developed at Fermilab. Current monitoring to 1 nA and remote disconnect are available on each channel. >

W.C. Carithers

Papers

A flexible 128 channel silicon strip detector instrumentation integrated circuit with sparse data readout

High voltage control and monitoring system for proportional chambers