A unique word and/or a receive phase in the demodulator in a multi-phase signal and/or a multi-level signal is detected by obtaining a plurality of correlation values, performing linear calculations for those correlation values to provide a correlation pattern, and looking at a table if this pattern coincides with one of the predetermined patterns. The invention is useful even when a received signal quality is poor and/or the length of the unique word is short. A plurality of unique word, together with received phase are also recognized by the present invention.

A unique word detection system

An extended length digital correlator threshold circuit for (N·Mit correlation using N M-bit correlators is disclosed. For the exemplary case where N=2, the digital correlator threshold circuit comprises: a first circuit for storing a preselected code word having first and second digital code portions; a first correlator responsive to the first digital code portion and an input digital data stream passing therethrough for periodically producing a first multibit number representative of the number of bit agreements between the bits in the digital data stream and the bits in the first digital code portion; a second correlator responsive to the second digital code portion and the digital data stream passing therethrough from the first correlator for periodically producing a second multibit number representative of the number of bit agreements between the bits in the digital data stream from the first correlator and the bits in the second digital code portion; and a second circuit responsive to said first and second multibit numbers for generating an output signal when the combined number of bit agreements in both of the first and second multibit numbers is at least equal to a preselected threshold number.

System for (N•M)-bit correlation using N M-bit correlators

High speed serial data bits of a data stream are received, stored, shifted and compared in parallel to bit contents of a known correlation word. For each bit match a known signal change is provided on a common terminal. High speed current or voltage changes on the common terminal are proportional to the number of matching bits and are monitored to detect presence of the correlation word in the received data stream. The circuit has minimum number of components and built-in temperature compensation.

High speed correlation circuit and method

A digital programmable packet switch synchronizer receives a digital input data stream which includes a unique digital word. The unique digital word is stored in the synchronizer in a random access memory. A group of the most recently received data bits are stored in memory along with a blanker bit for each data bit. The blanker bit determines the valid or invalid status of the data bit. During each bit period of the incoming data stream, the stored data bits are serially compared with the stored unique word. A count is made of the number of noncomparisons between the stored data bits and the stored unique word bits when the data bit is valid. If the number of noncomparisons does not exceed a programmed error limit, an output signal is generated to indicate detection of the unique word. A similar count is carried out for detection of the inverse to the unique word. The number of invalid blanker bits for the data bits is also counted and if this count exceeds a programmed limit, the detection of the unique word is inhibited. When the positive of the unique word is detected, the incoming data is transmitted to an output terminal with a positive logic sense. But if the inverse of the unique word is detected, the incoming data is inverted and transmitted to the output terminal. In either case, the incoming data is transmitted to the output terminal with the correct polarity.

Digital programmable packet switch synchronizer

A method and apparatus are disclosed for detecting, in a plurality of stages of a matched filter, a binary convoluted coded signal having a plurality of code levels ranging from a low level, high repetition rate code to a high level, low repetition rate code, in which each filter stage of the matched filter is used to store elements of the convoluted coded signal in a memory such as a tapped delay line. The stored code is then tapped at intervals defined by the convoluted code to obtain a set of samples. The samples are then multiplied, each with a polarity coefficient determined by the convoluted code level at the tap locations resulting in translated samples. The samples are then summed in an adder to obtain an output signal. The output is connected to the input of the memory of a next filter stage of the matched filter and the sequence is continued for all the code levels in the signal.

Method and apparatus for detecting a binary convoluted coded signal

A digital data correlator is provided which detects the presence of a particular sequence, or correlating pattern, of binary data bits in a serial binary data stream, is tolerant of data errors, and is adjustable to accept different numbers of data errors. The correlator includes a shift register of the CMOS type, a plurality of inverters of the CMOS type connected to selected outputs of the register at which bits of a particular logic value are expected for a properly positioned correlating pattern in the register, and a plurality of like-valued resistances coupled to the outputs of the register and to the inverters. Erroneous bits in the register cause an error voltage to be produced at a common node point coupled to the resistances. The value of the error voltage is compared in a comparator against a threshold reference voltage of a value related to an acceptable number of erroneous bits. An output of a first logic value is produced by the comparator when the number of erroneous bits in the register exceeds the acceptable number, and an output of a second logic value is produced by the comparator when the number of erroneous bits in the register is equal to or less than the acceptable number. The digital data correlator further includes circuitry capable of altering the number of erroneous bits that will be tolerated or accepted by the correlator.

W. Douglas Strubeck

Papers

Digital data correlator