An efficient real-time implementation of digital filtering algorithms using a multiprocessor system in a ring network is investigated. This method is based on a parallel block processing approach, where a continuously supplied input data is divided into blocks, and the blocks are processed concurrently by being assigned to each processor in the system. This approach requires only a simple interconnection network and reduces significantly the number of communications among the processors, making the system easily expandable and highly efficient. In addition, various digital signal processing algorithms can be implemented on the same multiprocessor system. The data dependency of the blocks to be processed concurrently brings on dependency problems between the processors. A systematic scheduling method has been developed by using a precedence graph for the analysis of the dependency relation. Methods for solving the dependency problems between the processors are also investigated. Implementation procedures and results for FIR, recursive, and adaptive filtering algorithms are illustrated. >

Multiprocessor implementation of digital filtering algorithms using a parallel block processing method

We describe a novel, expandable, multiple digital signal processor (DSP) architecture with a symbolic processing host. A multiprocessor board, called Odyssey, based on this architecture has been developed to combine symbolic and real-time digital signal processing in a single computing environment. Some of the key features of the board are: 20 million multiply/accumulates per second, 512K bytes of data space, and expandability to 16 boards on a NuBus host. The DSPs used are the TMS32020 signal processing chips developed by Texas Instruments, and the host is Texas Instruments' Explorer, a LISP machine workstation. This provides environment to perform many intelligent signal processing tasks by associating meaningful relationships between quantitative (signal processing) and qualitative (symbolic processing) entities to develop inferences using expert system technology. Applications such as grammar-driven connected speech recognition, neural network simulation, EEG analysis, and generation of speech from general English text with natural language processing are some of the tasks that can utilize the computational power of the multiple DSP and/or the associated symbolic processing capabilities. Software development tools to implement applications include the device driver to facilitate communication between the host processor and the Odyssey board, a unique window-based debugger resident on the Explorer that allows for simultaneous state display of all the processors on the board, a FORTH interpreter for high-level language programming, and a cross-assembler/linker for assembly level programming.

Multiple digital signal processor environment for intelligent signal processing

In an effort to produce more efficient means of transforming new algorithm concepts into working models, this paper describes the development of a digital signal processing workstation accepting input entirely in graphic form. This Graphic Oriented Signal Processing Language (GOSPL) accepts flow graph information in block diagram form using a mouse input device. The researcher uses the mouse to describe graph connections and create function blocks in the flow graph by selecting them from a menu. The system executes a broad class of flow graphs and provides virtual instruments to monitor signals throughout the graph during real-time execution.

Graphic oriented signal processing language-GOSPL

Speech recognition algorithms employing a similarity measure between the input speech utterance and the stored reference patterns to determine recognition of a word/sentence are computationally intensive. The instantaneous vocabulary size that can be handled in real-time is relatively small. This limitation can be alleviated by either using multiple programmable processors or by using special purpose hardware to handle the computation-intensive tasks. In a research environment the former approach is preferred, because improvements to the algorithm can rapidly be incorporated and their effects studied in real-time. Texas Instruments has developed a multiple-processor architecture based on the TMS32020 DSP, called Odyssey, that interfaces with Explorer, a symbolic computer. This paper addresses the issues involved in partitioning and allocating tasks in a multiple-processor environment to maximise throughput, and discusses the implementation of a grammar-driven speaker-dependent connected-word recognizer (GDCWR) as an example application that uses the power of multiple processors.

Connected word recognizer on a multiprocessor system

As digital signal processor (DSP) devices become more prevalent, a need has developed to support not only dedicated, single device applications, but also to provide system architectures which support multiple DSP requirements. Multiple, or parallel. DSP systems can quickly leverage the power of single devices into powerful processors capable of solving the most complex signal processing problems. This paper describes a specific implementation of a multiple DSP system which is being used to solve a problem in speech recognition.

A parallel signal processor system

This paper describes a real-time implementation of a variable rate baseband speech coding algorithm. The implementation is achieved using the Speech Command System (SCS) option available with the Texas Instruments Professional Computer (TIPC). The SCS consists of a peripheral speech board and related interface software. The central processor on the peripheral speech board is TI's new signal processing microcomputer TMS32010. The implementation works real-time with an average bit rate of the 9600 bits/sec.

W. Gass

Papers

A parallel signal processor system

Real-time 9600 bits/sec speech coding on the TI Professional Computer