Hybrid computing systems, consisting of a CPU server coupled with a Field-Programmable Gate Array (FPGA) for application acceleration, are today a common facility in datacenters and clouds. FPGAs can deliver tremendous improvements in performance and energy efficiency for a range or workloads, but development and deployment of FPGA-based applications remains cumbersome, leading to recent work which replicates subsets of the traditional OS execution environment (virtual memory, processes, etc.) on the FPGA. In this paper we ask a different question: to what extent do traditional OS abstractions make sense in the context of an FPGA as part of a hybrid system, particularly when taken as a complete package, as they would be in an OS? To answer this, we built and evaluated Coyote, an open source, portable, configurable “shell” for FPGAs which provides a full suite of OS abstractions, working with the host OS. Coyote supports secure spatial and temporal multiplexing of the FPGA between tenants, virtual memory, communication, and memory management inside a uniform execution environment. The overhead of Coyote is small and the performance benefit is significant, but more importantly it allows us to reflect on whether importing OS abstractions wholesale to FPGAs is the best way forward.

/pdf/do-os-abstractions-make-sense-on-fpgas-4pt494urjm.pdf

Do OS abstractions make sense on FPGAs

Field Programmable Gate Array (FPGA) has become an efficient accelerator for convolutional neural network (CNN) inference due to its high performance and flexibility. To further improve the performance of CNN inference on FPGAs, an Intellectual Property core (IP core) called Deep Learning Processor Unit (DPU) is released by Xilinx. Unlike previous FPGA-based hardware designs focusing on specific functions or CNNs, the DPU IP supports ample basic functions of deep learning, and the developers can take advantage of DPUs to accelerate CNN inference conveniently. In DPU-based CNN acceleration platform, an encapsulated scheduler plays a crucial role in task scheduling between heterogeneous ARM and multiple DPUs. However, the current scheduler is unsatisfactory because its low schedule efficiency. This paper thus presents a high performance task assignment framework built upon Xilinx hybrid CPU-FPGA MPSoC devices. We first evaluate the main causes of low schedule efficiency problem. Then, we explore the scheduler rules and improve shedule efficiency through purposeful observations and analysis. Finally, we integrate our optimizations, and propose an efficient task assignment framework to maximize performance on DPU-based CNN acceleration platform. Experimental results on Xilinx Zynq UltraScale+ MPSoC zcu104 show that our efficient task assignment framework significantly boosts schedule efficiency for small-scale CNNs (from 36% to 70%), medium-scale CNNs (from 65% to 95%), and large-scale CNNs (from 77% to 99%) compared with original schedule strategy.

/pdf/an-efficient-task-assignment-framework-to-accelerate-dpu-302lektulh.pdf

An Efficient Task Assignment Framework to Accelerate DPU-Based Convolutional Neural Network Inference on FPGAs

We study conversational group detection in varied social scenes using a message-passing Graph Neural Network (GNN) in combination with the Dominant Sets clustering algorithm. Our approach first describes a scene as an interaction graph, where nodes encode individual features and edges encode pairwise relationship data. Then, it uses a GNN to predict pairwise affinity values that represent the likelihood of two people interacting together, and computes non-overlapping group assignments based on these affinities. We evaluate the proposed approach on the Cocktail Party and MatchNMingle datasets. Our results suggest that using GNNs to leverage both individual and relationship features when computing groups is beneficial, especially when more features are available for each individual.

Conversational Group Detection with Graph Neural Networks

This paper discusses the use of deep convolutional neural networks for radar target classification. In this paper, three parts of the work are carried out: firstly, effective data enhancement methods are used to augment the dataset and address unbalanced datasets. Second, using deep learning techniques, we explore an effective framework for classifying and identifying targets based on radar spectral map data. By using data enhancement and the framework, we achieved an overall classification accuracy of 0.946.  In the end, we researched the automatic annotation of image ROI (region of interest). By adjusting the model, we obtained a 93% accuracy in automatic labeling and classification of targets for both car and cyclist categories.

/pdf/deep-learning-based-classification-of-radar-spectral-maps-3fbojkum6l.pdf

Deep Learning Based Classification of Radar Spectral Maps

Handwriting recognition is an important area in pattern recognition. For many years, Tai Le has been widely used in Southwest China and Southeast Asia, which makes it of great interest for recognition research. The characteristics of the highly similar characters in Tai Le, such as its large proportion of similar characters and the randomness of its writing, bring great challenges to the task of recognition. In this paper, a method based on ensemble deep learning for offline handwritten Tai Le characters is proposed. First, the handwritten Tai Le character dataset SDH2019.2 was constructed and preprocessed. Then, an ensemble deep convolutional neural network (EDCNN) model was constructed by using a stacking strategy. Thirty deep neural network (DNN) and logistic regression algorithms were integrated into a strong Tai Le classifier by stacking. Experiments showed that the proposed model is competitive with the base DNN model and other ensemble models. The results indicate that the performance of Tai Le recognition by the stacking ensemble-based deep neural network model is high, with an accuracy of 98.85%. Additionally, its precision, recall and F1-score of 98.87%, 98.85% and 98.85%, respectively, are superior to those of other classic neural network models. To verify the general applicability of EDCNN, its effectiveness was also verified by recognizing MNIST handwritten digits and Devanagari handwritten characters.

Offline handwritten Tai Le character recognition using ensemble deep learning

Deep learning is greatly promoting the fast development of artificial intelligence In the image classification area, the recognition rate and inference performance become the main challenges in the real application Recently, residual network (ResNet) has shown a competitive accuracy and nice convergence behaviors in deep neural networks In this paper, we are devoted to accelerate this promising framework in the inference application on FPGA (Field Programmable Gate Array) using OpenCL programming language Firstly, a supplemented deep learning accelerator is constructed to realize the residual function in ResNet Secondly, our construction reschedules three on-chip buffers in order to store the feature data and to stream it to processor elements alternately In addition, we also implement data parallel and pipeline execution such that the filter parameters can be synchronously processed with the image data on FPGA Moreover, we exploit a convertor to transform any ResNet in CAFFE framework into FPGA platform It can generate the FPGA head files using its original prototxt files through the dictionary function of Python The experiment result analysis shows that our acceleration has a competitive performance while maintaining the high accuracy rate Finally, we provide a solution to accelerate any construction of ResNet using OpenCL programming language on FPGA

FPGA accelerates deep residual learning for image recognition

The application discloses an AES symmetric encryption and decryption method and system based on a heterogeneous acceleration platform. The method comprises the following steps: a CPU terminal executes a host terminal executable file, sends a to-be-processed data set and a starting control signal to an FPGA terminal and acquires a processing result obtained by the FPGA terminal; and the FPGA terminal executes a Kernel executable file under the control of the starting control signal to encrypt or decrypt data in the to-be-processed data set according to a target algorithm so as to obtain a corresponding processing result, wherein the target algorithm is an AES symmetric encryption or decryption algorithm, the host terminal executable file and the Kernel executable file are executable files generated based on a host terminal program and a Kernel program, respectively, and the host terminal program and the Kernel program are programs generated by carrying out high-grade language description on the target algorithm by virtue of OpenCL. By executing the Kernel executable file on the FPGA terminal, the parallel processing time required in the AES symmetric encryption or decryption process can be substantially reduced, and the AES symmetrical encryption and decryption speeds are obviously increased.

AES symmetric encryption and decryption method and system based on heterogeneous acceleration platform

The invention discloses a data processing method based on an SHA512 algorithm. A processor carries out operation such as digit filling on to-be-processed data and then sends the data to an FPGA development board; the data is processed by a four-wheel packet compression iterative algorithm pre-stored in the FPGA development board; and the processor obtains a processing result, thereby obtaining a final Hash value. The core four-wheel packet compression iterative algorithm with the highest operation quantity in the SHA512 algorithm is processed by the FPGA rather than the processor, so the resource consumption in the processor can be reduced. The invention also discloses a data processing device based on the SHA512 algorithm and a data processing system based on the SHA512 algorithm. The device and the system also have the technical effects.

Data processing method, device and system based on SHA512 algorithm

The invention discloses an SM4 symmetric encryption and decryption method based on a heterogeneous acceleration platform and an SM4 symmetric encryption and decryption system thereof. The method comprises the steps that a CPU side operates a host side executable file so as to transmit a data set to be processed and a start control signal to an FPGA side and acquire the processing result obtained by the FPGA side; and the FPGA side operates a Kernel executable file under the control of the start control signal so as to perform data encryption or decryption processing corresponding to a target algorithm on the data set to be processed to obtain the corresponding processing result, wherein the target algorithm is an SM4 symmetric encryption or decryption algorithm, the host side executable file and the Kernel executable file are the executable files generated on the basis of the host side program and the Kernel program, and the host side program and the Kernel program are the programs generated by using OpenCL to perform high-level language description for the target algorithm The Kernel executable file is operated on the FPGA side so that the time required for parallel processing in the SM4 symmetric encryption process or decryption process can be greatly reduced, and the SM4 symmetric encryption and decryption speed can be obviously enhanced.

SM4 symmetric encryption and decryption method based on heterogeneous acceleration platform and SM4 symmetric encryption and decryption system thereof

The invention discloses an MD5 (Message-Digest Algorithm 5) calculation method and system and a computer readable storage medium for a CPU+FPGA (Central Processing Unit+ Field Programmable Gate Array)heterogeneous acceleration platform. The method comprises the following steps that: a host side sends data to be processed to the DDR (Double Data Rate) memory of an FPGA board card, and sets parameter information required for the operation of an FPGA side; the FPGA side carries out MD5 hash function calculation on the data to be processed, and stores an obtained calculation result to the DDE memory; and the host side obtains calculation result data from the DDR memory. By use of the method, through the FPGA side, according to the parameter information, the data to be processed is subjected to the MD5 hash function calculation, the obtained calculation result is stored to the DDR memory, the FPGA side can be used for accelerating the performance of a grouped-cycling operation, the execution performance of the MD5 hash function calculation is improved, the implementation efficiency of the MD5 hash function calculation is effectively improved, and development cost and periods can be reduced.

Wang Li

Papers

FPGA accelerates deep residual learning for image recognition

AES symmetric encryption and decryption method and system based on heterogeneous acceleration platform

Data processing method, device and system based on SHA512 algorithm

SM4 symmetric encryption and decryption method based on heterogeneous acceleration platform and SM4 symmetric encryption and decryption system thereof

MD5 (Message-Digest Algorithm 5) calculation method and system and computer readable storage medium