The Physical Unclonable Function (PUF) circuit generates a random, unclonable key by extracting random deviations of the manufacturing processes. In this paper, a delay ternary PUF (DT-PUF) circuit scheme based on Carbon Nanotube Field Effect Transistor (CNFET) is proposed. In this scheme, the two inputs and two outputs (2I2O) multi-value delay circuit and the multi-valued arbiter circuit is designed by the threshold controllable CNFET. Then, the ternary signals logic 0, logic 1 and logic 2 transmission delay path is realized by cascading multi-bit 2I2O multi-value delay circuits. Secondly, the delay deviation of the two identical transmission paths is set as the random source. With the help of ternary arbiter, the random delay competes to produce the unclonable ternary PUF output data. Finally, the proposed DT-PUF circuit is designed under 32nm CNFET standard model library, and the circuit is simulated and analyzed by HSPICE. Experiment results show that DT-PUF circuit has the correct logic function, and the distribution is 30.3%@logic 0, 36%@logic 1, 33.7%@logic 2, near ideal about 33.3%.

Design of Delayed Ternary PUF Circuit Based on CNFET

BiCMOS Circuits which have both advantages of CMOS circuits and bipolar Circuits have been paid more and more attention.A novel general structure and design method for pulse-triggered flip-flops based on BiCMOS technique are proposed and two kinds of D flip-flops according to the structure are presented.The results carried out by Hspice using TSMC 180nm show the proposed circuits have correct logic functions and advantages of high speed,low power and strong drive ability.Compared with existing designs,the proposed BiCMOS pulse-triggered D flip-flops consume much less power and have much smaller PDP.

A general structure for high-speed and low-power BiCMOS pulse-triggered flip-flops

This paper reviews, analyzes and proposes a new method for high frequency applications of carbon nanotube field effect Transistors (CNTFETs) with validation based of the simulation results for high frequency applications, which are promising technology for High-performance electronic devices. CNTFETs face several challenges due to their nanometer dimensions, including issues with leakage current, power consumption regulation, switching speed, and short channel effects like drain-induced barrier lowering (DIBL) and sub-threshold swing (SS). In this respect Low power CNTFET devices are of particular interest and will result in an enhanced and efficient battery life in modern portable smartphones and devices. With the increasing demand for high-speed and high-performance electronic devices, CNTFET technology is emerging as a promising field of research, especially in the context of 5G technology. Here, various methods, approaches, and strategies have been discussed to address the issues related to the performance of the device. By analyzing and discussing these new approaches published in the literature, researchers can identify the most effective strategies for improving the performance of electronic devices, including CNTFETs. Some of the new approaches that have been discussed in the literature including the use of novel materials for CNTFET Fabrication, such as graphene and other 2D materials, as well as the development of new device architectures that can reduce power consumption and improve switching speed. Other strategies include optimizing the gain, doping concentration and channel length of CNTFETs with respect to the operating frequency along with a dedicated emphasis on exploring the nascent techniques to reduce leakage current and minimize short-channel effects. A general conclusion is also presented that is based on comparison of contemporary technologies. Researchers in the field of electronic solid state devices, especially those working on CNTFET circuit design and fabrication, could benefit from these findings. Index Terms— Carbon Nanotubes, field-effect transistor. 

Carbon Nanotube Field Effect Transistors: An Aspect of Low Power and High Frequency Applications of CNTFETs

By analyzing the principle and structure of A novel pulsed reversible counter are designed with Carbon Nanotube Field Effect Transistors(CNFET). Firstly, the ternary pulsed D trigger with reset port and set port is designed by using switch-signal theory. Then, the up/down circuit, carry/borrow controlled circuit are designed, respectively. Based on the design above, the four bit ternary reversible counter with CNFET is achieved. After simulating by HSPICE, the result show that proposed circuit decreased by 36.4 percent compare with counter based on JKL flip-flop.

Design of ternary pulsed reversible counter based on CNFET

This paper reviews, analyzes and proposes a new method for high frequency applications of carbon nanotube field effect Transistors (CNTFETs) with validation based of the simulation results for high frequency applications, which are promising technology for High-performance electronic devices. CNTFETs face several challenges due to their nanometer dimensions, including issues with leakage current, power consumption regulation, switching speed, and short channel effects like drain-induced barrier lowering (DIBL) and sub-threshold swing (SS). In this respect Low power CNTFET devices are of particular interest and will result in an enhanced and efficient battery life in modern portable smartphones and devices. With the increasing demand for high-speed and high-performance electronic devices, CNTFET technology is emerging as a promising field of research, especially in the context of 5G technology. Here, various methods, approaches, and strategies have been discussed to address the issues related to the performance of the device. By analyzing and discussing these new approaches published in the literature, researchers can identify the most effective strategies for improving the performance of electronic devices, including CNTFETs. Some of the new approaches that have been discussed in the literature including the use of novel materials for CNTFET Fabrication, such as graphene and other 2D materials, as well as the development of new device architectures that can reduce power consumption and improve switching speed. Other strategies include optimizing the gain, doping concentration and channel length of CNTFETs with respect to the operating frequency along with a dedicated emphasis on exploring the nascent techniques to reduce leakage current and minimize short-channel effects. A general conclusion is also presented that is based on comparison of contemporary technologies. Researchers in the field of electronic solid state devices, especially those working on CNTFET circuit design and fabrication, could benefit from these findings. Index Terms— Carbon Nanotubes, field-effect transistor.

A novel single-edge explicit pulsed JKL flip-flop (S-JKL) and dual-edge explicit pulsed JKL flip-flop (D-JKL) are designed with Carbon Nanotube Field Effect Transistor (CNFET). Firstly, a single-edge pulsed generator (S-PG) is designed. Then combined with a ternary JKL latch, a S-JKL is obtained; D-JKL is designed by replacing S-PG with double-edge pulsed generator (D-PG). The circuits possess the character of high speed and low power by employing CNFET. The scheme is simulated by HSPICE, and the results show that the designed ternary explicit pulsed JKL flip-flop has correct logic function and low power consumption.

Novel low-power ternary explicit pulsed JKL flip-flop based on CNFET

A novel single-edge pulse generator (S-PG) and a dual-edge pulse generator (D-PG) are designed with Carbon Nanotube Field Effect Transistor (CNTFET). In order to generate pulse signal alternately, the output is controlled by delayed clock signal. The single-edge pulse generator without pseudo PMOS can reduce power consumption. The dual-edge pulse generator with same setup time on rising and falling clock edges can achieve the minimum data-to-output delay in pulse flip-flop (P-FF). Simulations of pulse generators are performed by HSPICE software and good agreement between the logical analysis and simulation results is achieved. With low power consumption and short pulse delay, the pulse generators conform to CNTFET circuits.

Wang Qian

Papers

Novel low-power ternary explicit pulsed JKL flip-flop based on CNFET

Design of explicit-pulse generators with CNTFET