The present disclosure provides an integrated circuit chip device and a related product. The integrated circuit chip device includes: a primary processing circuit and a plurality of basic processing circuits. The primary processing circuit or at least one of the plurality of basic processing circuits includes the compression mapping circuits configured to perform compression on each data of a neural network operation. The technical solution provided by the present disclosure has the advantages of a small amount of computations and low power consumption.

Integrated circuit chip device and related product

The invention discloses a digital-analog hybrid charge domain neuron circuit based on the CMOS process. The neuron circuit is characterized by comprising a 4bit DAC, a neuron synapse circuit, an 8bitADC, an activation function circuit and a sequential circuit, wherein the 4bit DAC, the neuron synapse circuit, the 8bit ADC and the activation function circuit are sequentially connected, and the sequential circuit is connected with the 4bit DAC, the neuron synapse circuit, the 8bit ADC and the activation function circuit. The neuron circuit has advantages of mature process, low cost, low power consumption and high universality.

Digital-analog hybrid charge domain neuron circuit based on CMOS process

The invention discloses a digital-analog hybrid neural network chip architecture. The architecture comprises a two-dimensional SRAM module, an analog synaptic circuit, a nerve cell circuit, an AER communication module, and a master control digital unit. The two-dimensional SRAM module is taken as a storage unit of neural network connection relation and a synaptic weight value. The analog synaptic circuit and the nerve cell circuit respectively consist of an MOSFET circuit working in a subthreshold section. The AER communication module serves as the input and output interfaces of a chip, and employs an AER protocol for communication. All control circuits in the architecture are synchronous digital circuits. The architecture is low in power consumption, is high in degree of parallelism, and can achieve a neural network algorithm in a reasonable chip area, wherein the neural network algorithm is more complex in nerve cell functions, is larger in network scale, and is more flexible in connection.

Wang Zhehong

Papers

Digital-analog hybrid neural network chip architecture