Improved approaches to providing thermal and power management for a computing device are disclosed. These approaches facilitate intelligent control of a processor's clock frequency and/or a fan's speed so as to provide thermal and/or power management for the computing device.

Thermal and power management for computer systems

Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

Processor chip having on-chip circuitry for generating a programmable external clock signal and for controlling data patterns

A dynamically switchable clock system having a symmetrical output signal includes a frequency doubler which couples the input frequency to provide greater resolution and synchronization of an output signal to an input signal in the frequency divider and the facility to handle odd divides as even divides at double frequency, a counter controlled by a divisor select signal, first and second compare circuits which compare against the preprogrammed count for division, the compare circuits receiving an input from the divisor select circuits, and having outputs to a counter reset line and to an output clock S/R latch which provides the frequency divided symmetrical output signal.

Symmetric clock system for a data processing system including dynamically switchable frequency divider

This variable clock dividing circuit is provided with a plurality of dividers coupled in succession. A first of the dividers divides the basic clock by a predetermined dividing ratio and provides an output clock signal to the next divider in succession, while the last divider receives an output clock signal from the next to last divider. The dividing circuit selectively outputs one of the output block signals from the dividers using a switching circuit. A phase synchronization circuit synchronizes the phase of the clock input to the plurality of dividers based on the basic clock. The phase synchronization circuit further comprises a buffer to delay the basic clock before inputting it to the first divider, and a plurality of AND gates. Each of the AND gates corresponds corresponds to the second to last dividers and receives the basic clock and the outputs from all the preceding dividers.

Variable clock dividing circuit

A circuit and method for determining the operating performance of an integrated circuit which may be used to screen integrated circuits prior to sale or delivery, or to optimize the frequency of the integrated circuit during use. The circuit employs a comparison circuit to compare a first time of arrival of a clock pulse, which is propagating through the integrated circuit with a second time of arrival of the clock signal at a second input. The comparison circuit produces an output signal which may be used to reject or accept the integrated circuit, or to automatically adjust the frequency to minimize the delay.

Circuit and method for determining the operating performance of an integrated circuit

A clock pulse generator for a one-chip microprocessor permits the microprocessor to be operated on two different power sources by effectively using a single source of clock pulses, a clock pulse divider and gate circuits to gate a specific sequence of pulses to the microprocessor. The period of a slowest clock pulse signal after division is integrally related to the periods of the faster clock pulse signals so that the pulse signals are synchronously provided.

Variable frequency clock pulse generator for microcomputer

The output of a single source of pulses is sequentially frequency divided (2 to 5) and gate circuits (6a to 9b) are arranged so that a selected one of the frequency-divided pulse signals can be supplied to an output terminal (10a, 10b).

Generating clock pulses

PURPOSE:To obtain block signals which differ in frequency and have excellent phase relation by controlling the switching of gate circuits during instruction execution at need and supplying a clock signal of desired frequency to a central processor. CONSTITUTION:Plural kinds of frequency division output signals are obtained from a clock signal from a clock oscillator and supplied to clock signal output terminals 10a and 10b through the gate circuits 6a and 6b,...9a and 9b. Then the gate circuits 6b,...9a and 9b are switched during instruction execution at need to supply the clock signal of desired frequency to the central processor. Consequently, low-speed clock signals, e.g. frequency-division output signals are generated at the time of a low source voltage to secure the operation even at the time of the low source voltage, and the power consumption is reduced by performing low-voltage driving in case of a power failure, etc.

Watanabe Nobuhisa

Papers

Variable frequency clock pulse generator for microcomputer

Generating clock pulses

Clock generating circuit for microcomputer