Showing papers by "Wayne Luk published in 1995"
01 Sep 1995
TL;DR: An overview of a prototype hardware compiler which compiles a design expressed in the Ruby language into FPGAs, and the features of two important modules, the refinement module and the floorplanning module, are discussed and illustrated.
Abstract: This paper presents an overview of a prototype hardware compiler which compiles a design expressed in the Ruby language into FPGAs The features of two important modules, the refinement module and the floorplanning module, are discussed and illustrated Target code can be produced in various formats, including device-specific formats such as XNF or CFG, and device-independent formats such as VHDL The viability of our floorplanning scheme is demonstrated by a compiler backend for Algotronix's CAL1024 FPGAs The implementation of a priority queue is used to illustrate our approach
34 citations
19 Apr 1995
TL;DR: A declarative framework that supports incremental design and validation of custom computers and the use of the framework in producing a priority queue implementation using Algotronix CAL devices is presented.
Abstract: Incremental methods can be used to produce implementations rapidly and to facilitate multi-level design optimisation. This paper describes a declarative framework, based on the language Ruby, that supports incremental design and validation of custom computers. The key elements of the approach include parameterised descriptions, design transformation and data refinement. Several priority queue designs are employed to illustrate our techniques and the computer-based tools; we also present the use of our framework in producing a priority queue implementation using Algotronix CAL devices.
22 citations
01 Sep 1995
TL;DR: Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware that includes a transputer closely-coupled to a Field-Programmable Gate Array (FPGA).
Abstract: Harp1 is a circuit board designed to exploit the rigorous compilation of parallel algorithms directly into hardware. It includes a transputer closely-coupled to a Field-Programmable Gate Array (FPGA). The whole system can be regarded as an instance of a process in the theory of Communicating Sequential Processes (CSP). The major elements themselves can also be viewed in the same way: both the transputer and the FPGA can implement many parallel communicating sub-processes. The Harp1 design includes memory banks, a programmable frequency synthesizer and several communication ports. The latter supports the use of parallel arrays of Harp1 boards, as well as interfacing to external hardware. Harp1 is the target of mathematical tools based upon the Ruby and occam languages, which enable unusual and novel applications to be produced and demonstrated correctly and rapidly; the aim is to produce high quality designs at low costs and with reduced development time.
20 citations
Book•
21 Aug 1995
TL;DR: The design of a new FPGA architecture migration of a dual granularity globally interconnected PLD architecture to a 0.5?
Abstract: The design of a new FPGA architecture.- Migration of a dual granularity globally interconnected PLD architecture to a 0.5? TLM process.- Self-timed FPGA systems.- The XC6200 FastMap(TM) processor interface.- The Teramac configurable compute engine.- Telecommunication-oriented FPGA and dedicated CAD system.- A configurable logic processor for machine vision.- Extending DSP-boards with FPGA-based structures of interconnection.- High-speed region detection and labeling using an FPGA-based custom computing platform.- Using FPGAS as control support in MIMD executions.- Customised hardware based on the REDOC III algorithm for high performance data ciphering.- Using reconfigurable hardware to speed up product development and performance.- Creation of hardware objects in a reconfigurable computer.- Rapid hardware prototyping of Digital Signal Processing systems using Field Programmable Gate Arrays.- Delay minimal mapping of RTL structures onto LUT based FPGAs.- Some notes on power management on FPGA-based systems.- An automatic technique for realising user interaction processing in PLD based systems.- Proper use of hierarchy in HDL-based high density FGPA design.- Compiling regular arrays onto FPGAs.- Compiling Ruby into FPGAs.- The CSYN verilog compiler and other tools.- A VHDL design methodology for FPGAs.- VHDL-based rapid hardware prototyping using FPGA technology.- Integer programming for partitioning in software oriented codesign.- Test standard serves dual role as on-board programming solution.- Advanced method for industry related education with an FPGA design self-learning kit.- FPGA implementation of a rational adder.- FPLD-implementation of computations over finite fields GF(2m) with applications to error control coding.- Implementation of Fast Fourier Transforms and Discrete Cosine Transforms in FPGAs.- Implementation of a 2-D fast Fourier transform on an FPGA-based custom computing machine.- An assessment of the suitability of FPGA-based systems for use in digital signal processing.- An FPGA prototype for a multiplierless FIR filter built using the logarithmic number system.- Bit-serial FIR filters with CSD coefficients for FPGAs.- A self-validating temperature sensor implemented in FPGAs.- Developing interface libraries for reconfigurable data acquisition boards.- Prototype generation of application specific embedded controllers for microsystems.- A hardware genetic algorithm for the traveling salesman problem on Splash 2.- Modular architecture for real-time astronomical image processing with FPGA.- A programmable I/O system for real-time AC drive control applications.- Reconfigurable logic for fault tolerance.- Supercomputing with reconfigurable architectures.- Automatic synthesis of parallel programs targeted to dynamically reconfigurable logic arrays.- Prototyping environment for dynamically reconfigurable logic.- Implementation approaches for reconfigurable logic applications.- Use of reconfigurability in variable-length code detection at video rates.- Classification and performance of reconfigurable architectures.
2 citations
17 Oct 1995
TL;DR: The framework is to support flexible hardware and software partitions, so that designs can be customised to changing performance requirements and resource availability and facilitate rapid design exploration, adaptation and evaluation.
Abstract: Electronic systems are increasingly implemented in a variety of hardware and software technologies. Designers of such systems face two challenges: to meet specified performance targets at the lowest cost, and to complete their designs in the shortest time. This paper outlines a framework currently under development that should help designers to overcome these challenges. The framework is to support flexible hardware and software partitions, so that designs can be customised to changing performance requirements and resource availability. The framework should also facilitate rapid design exploration, adaptation and evaluation, as well as systematic design refinement, validation and documentation.
2 citations
02 Jan 1995
TL;DR: The use of Ruby, a language of relations and functions, for describing artificial neural networks and for implementing them in hardware is illustrated to enable designs to be rapidly realised and evaluated.
Abstract: Most artificial neural networks consist of one or more arrays of components, each of which is obtained by replicating a few simple processing elements connected together in a uniform manner. This paper illustrates the use of Ruby, a language of relations and functions, for describing such networks and for implementing them in hardware. Our objective is to enable designs to be rapidly realised and evaluated.