This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

Maximum and minimum of correlated Gaussian random variables arise naturally with respect to statistical static time analysis. It appears, however, that only approximations have been used in the literature to study the distribution of the max/min of correlated Gaussian random variables. In this paper, we would like to point out that the statistics literature has long established simple expressions for the exact distribution of the max/min. We provide some of the known expressions for the following: the probability density function, moment generating function, and the moments. We also provide two simple programs for computing the probability density functions of the max/min and an illustration of the results to statistical static time analysis.

/pdf/exact-distribution-of-the-max-min-of-two-gaussian-random-ivhd0vhfwb.pdf

Exact Distribution of the Max/Min of Two Gaussian Random Variables

Interconnect has become a primary bottleneck in integrated circuit design As CMOS technology is scaled, it will become increasingly difficult for conventional copper interconnect to satisfy the design requirements of delay, power, bandwidth, and noise On-chip optical interconnect has been considered as a potential substitute for electrical interconnect in the past two decades In this paper, predictions of the performance of CMOS compatible optical devices are made based on current state-of-art optical technologies Electrical and optical interconnects are compared for various design criteria based on these predictions The critical dimensions beyond which optical interconnect becomes advantageous over electrical interconnect are shown to be approximately one tenth of the chip edge length at the 22 nm technology node

Predictions of CMOS compatible on-chip optical interconnect

At current operating frequencies, inductive-coupling effects can be significant and should be included for accurate crosstalk-noise analysis. In this paper, an analytical framework to model crosstalk noise in coupled RLC interconnects is presented. The proposed model is based on transmission-line theory and captures high-frequency effects in on-chip interconnects. The new model is generic in nature and can be applied to asymmetric driver-and-line configurations for aggressor and victim wires. The model is compared against SPICE simulations and is shown to capture both the waveform shape and peak noise accurately. Over a large set of random test cases, the average error in noise-peak estimation is approximately 6.5%. A key feature of the new model is that its derivation and form enables physical insight into the total coupling-noise-waveform shape and its dependence on relevant physical-design parameters. Due to its simplicity and physical nature, the proposed model can be applied to investigate the impact of various physical-design optimizations (e.g., wire sizing and spacing, shield insertion) on total RLC coupled noise. The effectiveness of various existing noise-reduction techniques in the presence of mutual-inductance coupling is studied here. The obtained results indicate that common (capacitive) noise-avoidance techniques can behave quite differently when both capacitive and inductive coupling are considered together.

Modeling and analysis of crosstalk noise in coupled RLC interconnects

This paper shows that the worst case switching pattern that incurs the longest bus delay while considering the RLC effect is quite different from that while considering the RC effect alone. It implies that the existing encoding schemes based on the RC model may not improve or possibly worsen the delay when the inductance effects become dominant. A bus-invert method is also proposed to reduce the on-chip bus delay based on the RLC model. Simulation results show that the proposed encoding scheme significantly reduces the worst case coupling delay of the inductance-dominated buses

/pdf/rlc-coupling-aware-simulation-and-on-chip-bus-encoding-for-txuu6tw4iv.pdf

RLC Coupling-Aware Simulation and On-Chip Bus Encoding for Delay Reduction

/sup A/ new approach to handle inductance effects for multiple signal lines is presented. The worst-case switching pattern is first identified. Then a numerical approach is used to model the effective loop inductance (L/sub eff/) for multiple lines. Based on a look-up table for L/sub eff/, an equivalent single line model can be generated to decouple a specific signal line from the others to perform static timing analysis. Compared to the use of full RLC netlists for multiple lines, this approach greatly improves the computational efficiency and maintains accuracy for timing and signal integrity analysis. We apply these models to repeater insertion in critical paths and find that, for a single line, the RLC model minimizes delay with fewer number of repeaters than RC model. However, for multiple lines, we find that same number of repeaters is inserted for optimal delay according to both the RC and RLC models.

Weize Xie

Papers

Effective on-chip inductance modeling for multiple signal lines and application to repeater insertion