A phase-locked frequency synthesizer (10) having a voltage controlled oscillator (40), a divider circuit (60), and a sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation.

Fast phase-lock frequency synthesizer with variable sampling efficiency

A sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG 6) having variable efficiency Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation Also provided is protection circuitry to neutralize leakage of the input signal to the output of the circuit when a sample control signal is not present

Sample-and-hold phase detector circuit

A phase-locked loop circuit comprises first and second charge pumps which apply charge and discharge voltages to a control voltage generator. The control voltage generator applies a control voltage which is dependent on the charge and discharge voltages to a voltage controlled oscillator. The voltage controlled oscillator generates an oscillation frequency dependent on the control voltage. The oscillation frequency is compared with a reference frequency to detect a difference therebetween. The first charge pump supplies a charge or discharge voltage to the control voltage generator intermittently for a first period, and the second charge pump, in parallel with the first charge pump, supplies a charge or discharge voltage to the control voltage generator continually for a second period subsequently to the first period, so that a time by which the difference becomes zero is shortened by use of the second charge pump as compared to a case where the first charge pump is only used.

Phase-locked loop circuit

An improved frequency synthesizer utilizes a first order loop and sample-and-hold phase detector (20) with optimized gain to obtain very fast frequency locking characteristics. In addition, synchronization of the programming of the loop divider (34) and of the range shifting the voltage controlled oscillator (30) is also utilized. An adaptive loop filter (100) is provided to allow a first order loop to be used for lock acquisition and still maintain excellent noise performance after lock has been obtained.

Synchronized frequency synthesizer with high speed lock

A phase lock detector circuit is disclosed that generates delayed versions of both a reference clock signal and a synthesized clock signal. From the delayed signals, first and second control signals that are pulses are generated. The pulses are passed through respective delays of predetermined durations and then clocked into respective shift registers by the latched signal of the opposite input. The shift register outputs are logically combined and shifted into a third shift register. Outputs from the third shift register are logically combined to ascertain whether a phase-lock loop is phase lock. The lock detector circuit may include a lock-out circuit to disable the phase lock detector circuit upon detecting phase lock.

Digital lock detector for phase-locked loop

This invention concerns a circuit which decreases the time required for certain phase-locked loops to pull in, that is, the time for the frequency of the oscillator which the loop controls to go from some initial error to some specified smaller error. The circuit is utilized with a loop employing an integrating element in the loop filter in conjunction with a logic circuit for indicating out-of-lock condition plus the sign of the frequency error and utilizes a source of direct current (DC) which is connected to the loop filter so as to increase the rate of change of the correction signal to the controlled oscillator and thereby speed-up tuning of the oscillator to the desired frequency.

William F. Egan

Papers

Phase lock speed-up circuit