A computer system's multiple processors are managed as devices. The operating system accesses the multiple processors using processor device modules loaded into the operating system to facilitate a communication between an application requesting access to a processor and the processor. A device-like access is determined for accessing each one of the processors similar to device-like access for other devices in the system such as disk drives, printers, etc. An application seeking access to a processor issues device-oriented instructions for processing data, and in addition, the application provides the processor with the data to be processed. The processor processes the data according to the instructions provided by the application.

Managing a Plurality of Processors as Devices

One embodiment of the invention provides a firmware architecture which splits firmware modules to support safe updates of specific modules as well as supporting multiple different processors. A firmware image is partitioned into several different binaries based on their update requirements and processor/platform dependence. A firmware interface table enables safe updates by enabling the option of redundant copies of specific modules as well as supporting systems with different and/or multiple processor types, mixed processors from the same family, and/or fault resilient firmware updates.

Firmware architecture supporting safe updates and multiple processor types

A method for sharing firmware across heterogeneous processor architectures. Respective sets of firmware are stored on a platform, including a first set of native firmware designed to execute on a first processor, a second set of native firmware designed to execute on a second processor; and a third set of firmware written in an intermediate language that may be processed via respective virtual machines executing on the first and second processors. The intermediate language is processor instruction set independent, while the native firmware is specific to the instruction sets of each of the first and second processors.

Method for sharing firmware across heterogeneous processor architectures

A method, apparatus and computer-usable medium are presented for loading firmware onto multiple processors. A firmware controller is coupled to multiple processors and a firmware memory. A service processor, by controlling the operation of the firmware controller, selects one or more of the multiple processors. Under the control of the service processor, the firmware controller sends firmware from the firmware memory to each of the selected processors, either sequentially or simultaneously. If one of the selected processors fails to fully execute the firmware from the firmware memory, the firmware controller notifies the service processor of that failure as well as the particular memory address in the firmware where the failure occurred.

Booting multiple processors with a single flash ROM

A task queue manager manages the task queues corresponding to virtual devices. When a virtual device function is requested, the task queue manager determines whether an SPU is currently assigned to the virtual device task. If an SPU is already assigned, the request is queued in a task queue being read by the SPU. If an SPU has not been assigned, the task queue manager assigns one of the SPUs to the task queue. The queue manager assigns the task based upon which SPU is least busy as well as whether one of the SPUs recently performed the virtual device function. If an SPU recently performed the virtual device function, it is more likely that the code used to perform the function is still in the SPU's local memory and will not have to be retrieved from shared common memory using DMA operations.

Task queue management of virtual devices using a plurality of processors

A system, a method of operating the system and a system firmware. The system includes a processor and a system firmware including a plurality of customized firmware parts, with each firmware part performing system firmware functions required for and customized to only a subset of a plurality of types of processors which are operational when connected to the system, and a processor identification device, coupled to the system, which identifies which subset of the plurality of types of processors is connected to the system and in response to the identification of the type of connected processor, causes a customized firmware part corresponding to the identified types of processor to be executed by the processor.

William J. Clem

Papers

Arrangements having firmware support for different processor types