A semiconductor device includes capacitors connected in parallel. Electrode active portions and a discharge active portion are defined on a semiconductor substrate, and capping electrodes are disposed respectively on the electrode active portions. A capacitor-dielectric layer is disposed between each of the capping electrodes and each of the electrode active portions that overlap each other. A counter doped region is disposed in the discharge active portion. A lower interlayer dielectric covers the entire surface of the semiconductor substrate. Electrode contact plugs respectively contact the capping electrodes through the lower interlayer dielectric, and a discharge contact plug contacts the counter doped region through the lower interlayer dielectric. A lower interconnection is disposed on the lower interlayer dielectric and contacts the electrode contact plugs and the discharge contact plug.

Semiconductor devices and methods of fabricating the same

The method for fabrication of openings in semiconductor devices to improve metal step coverage includes forming an active region over a substrate. A metal oxide layer is then formed over the source/drain region. An insulating layer is formed over the metal oxide layer. A photoresist layer is formed over the insulating layer, and patterned to form an opening, exposing a portion of the insulating. The insulating layer is then etched to expose a portion of the metal oxide layer. The photoresist layer is removed and the insulating layer is reflowed so as to form rounded corners at the opening of the insulating layer. The exposed portion of the metal oxide layer is removed to expose a portion of the active region.

Structure and method for contacts in cmos devices

A method of producing a semiconductor device comprising a bipolar transistor and a MOSFET (e.g., a Bi-MOS device), comprising the steps of: forming an insulating layer on an epitaxial silicon layer on a semiconductor substrate; forming a gate electrode; forming a base region; forming a PSG (an impurity containing glass) layer on the whole surface; carrying out a heat-treatment on the PSG to cause a softening and flow thereof (sloping ends of and flattening the PSG layer); opening collector, emitter, source and drain contact windows in the PSG layer and the insulating layer; forming a doped polysilicon layer over the contact windows with the formation of an emitter region; opening a base contact window; and forming metal (Al) electrodes.

Method of producing a semiconductor device by forming contacts after flowing a glass layer

A method for the manufacture of a large scale integration (LSI) MOS field effect transistor wherein a gate electrode is generated on a doped silicon substrate, source/drain regions are formed by ion implantation using the gate electrode as an implantation mask and the source/drain regions are shielded by means of an oxide layer extending to the sidewalls of the gate electrode so that the diffusion of the implanted source/drain regions under the gate electrode area are reduced. The specific improvement of the present invention involves applying a readily flowable silicate glass layer as a gate edge masking for the source/drain ion implantation after formation of the gate electrode, the silicate glass layer being applied by deposition from the vapor phase at a thickness such that the dopant ions in the subsequent source/drain ion implantation are still implanted into the zone near the surface under the silicate glass layer but ion implantation into the zones at the edges of the gate is suppressed.

Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation

An improved means and methods for forming multilayer metal electronic devices (10) where the intermetal dielectric (18) is formed of a three layer sandwich. The first metal layer (13) is covered with a dielectric layer (14) formed using plasma assisted oxide deposition or low pressure chemical vapor deposition. This first dielectric layer (14) is covered by a second dielectric layer (15) formed using a spun-on glass. The third dielectric layer (16) is formed by chemical vapor deposition or plasma deposition and is then covered with the second metal layer (17). Substantially improved step coverage is obtained and delamination between the intermetal dielectric (18) and the metal layers (13, 17) is avoided. The dielectric may be tapered-etched for contact holes.

Glass intermetal dielectric

A process for fabricating semiconductor devices including a field effect transistor has been described incorporating a substrate, a layer of thermal oxide having windows, a layer of polycrystalline silicon to form the gate electrode of field effect transistors and a first interconnection layer, a layer of silicon nitride, a layer of phosphorous doped silicon dioxide which have windows larger than the device windows and which is reflowed to smooth its upper surface over the polysilicon interconnections and to provide round edges, impurity regions formed on either side of the silicon gate electrode and bounded by the thermal oxide, forming openings to the drain and source regions, depositing a layer of metal over the substrate and defining the layer of metal to form a second layer of interconnections and also to provide ohmic contact to the source and drain regions. The process overcomes the problem of forming openings through a layer of phosphorous doped silicon oxide and further overcomes the problem of subsequent out diffusion of a drain and source impurity region at times when a layer of phosphorous doped silicon oxide is reflowed thus permitting shallow drain and source regions for short channel field effect transistors.

William M. Evey

Papers

Small dimension field effect transistor using phosphorous doped silicon glass reflow process